Senior Lead Design Engineer - RTL Design

Altera Semiconductor•San Jose, CA

About The Position

Altera is seeking a Senior Lead Design Engineer - RTL Design to provide hands-on technical leadership for the RTL architecture, design, integration, and delivery of next-generation FPGA and programmable SoC solutions. This is a technical leadership, individual-contributor role, setting technical direction across complex subsystems, product generations, and global engineering teams. The role leads implementation of high-performance, reusable RTL for programmable devices and platform solutions. It translates system and product requirements into robust microarchitectures, defines scalable implementation strategies, and guides work from early concept through RTL delivery, verification, implementation, hardware validation, and product readiness. The successful candidate brings deep RTL design expertise, sound systems judgment, and a high bar for quality, performance, power, and schedule. The position is based in San Jose, California. The stated salary range of $231,500–$330,000 USD applies to the Bay Area, California; actual salary may vary based on location and job-related factors. Incentive opportunities are offered based on individual and company performance. The company uses artificial intelligence to screen, assess, or select applicants. Applicants must be eligible for any required U.S. export authorizations.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
15+ years of relevant experience in FPGA, ASIC, SoC, or semiconductor product development.
Demonstrated technical leadership delivering complex digital designs from architecture and microarchitecture through RTL, verification, integration, implementation, and post-silicon or hardware validation.
Deep hands-on expertise in Verilog and/or SystemVerilog RTL development, synthesis, lint, CDC/RDC, formal or equivalence checking, timing constraints, and implementation-aware design practices.
Proven experience designing high-performance digital subsystems, such as network or data-processing pipelines, memory controllers or memory subsystems, on-chip interconnect, traffic-management logic, PCIe/CXL, Ethernet, high-speed interfaces, or programmable acceleration engines.
Strong understanding of architectural and RTL-level tradeoffs involving bandwidth, latency, congestion, buffering, throughput, power, area, timing, and reliability.
Experience leading design execution across multiple functional blocks or complex subsystem integration, including technical planning, risk management, schedule alignment, and prioritization.
Demonstrated ability to collaborate and influence across architecture, design verification, physical design, DFT, CAD, firmware/software, system validation, and product engineering organizations.
Strong written and verbal communication skills, including the ability to communicate design intent, technical risks, and recommended solutions to diverse audiences.

Nice To Haves

Advanced degree.
Experience designing RTL for FPGA architectures, programmable-logic devices, configurable interconnect, SmartNICs, IPUs, SoCs, or data-center acceleration platforms.
Experience building, maintaining, or deploying reusable RTL IP across multiple products, technology nodes, or programs.
Experience with high-bandwidth memory architectures, packet buffering, lookup or classification engines, flow control, or high-speed connectivity subsystems.
Experience with FPGA prototyping, emulation, silicon bring-up, post-silicon debug, or performance optimization.
Proficiency in scripting and workflow automation using Python, Tcl, Perl, or shell.
A record of technical leadership through patents, publications, standards contributions, or sustained methodology innovation.

Responsibilities

Lead RTL architecture, microarchitecture, and implementation for complex FPGA, programmable SoC, and infrastructure-class subsystems, with emphasis on high-throughput datapaths, memory access, interconnect, packet or data processing, and programmable acceleration.
Own RTL design for critical blocks and subsystem integrations, ensuring code is reusable, synthesizable, scalable, testable, and aligned to performance, power, area, and timing objectives.
Define design specifications, interface contracts, clocking and reset strategies, performance targets, and implementation plans aligned with architecture, verification, physical design, firmware, software, and product requirements.
Drive technical tradeoffs involving throughput, latency, bandwidth, buffering, power, area, timing, reliability, scalability, cost, and schedule; identify and mitigate architectural and execution risks early.
Establish and advance RTL design methodologies, including coding standards, lint, CDC/RDC, synthesis, formal checks, automation, and design-review practices.
Partner with design verification to shape verification strategy, review test plans and coverage, triage failures, and drive closure of complex pre-silicon issues.
Collaborate with physical design, CAD, DFT, emulation, FPGA prototyping, board, firmware, software, and post-silicon teams to preserve RTL intent through implementation, timing closure, validation, and product delivery.
Lead root-cause analysis and resolution of complex design, integration, performance, and system-level issues using disciplined debugging and data-driven decision-making.
Provide technical mentorship and RTL leadership across teams through architecture reviews, RTL/code reviews, and constructive guidance to engineers.
Influence design roadmaps and collaborate with internal teams and external partners on reusable IP, EDA capabilities, and implementation approaches.