ASIC/RTL Design Engineer 5

TekWissen • San Jose, CA

1d • Onsite

About The Position

The ASIC/RTL Design Engineer will build behavioral models of analog and mixed-signal circuits in SystemVerilog for use in a SystemVerilog UVM verification environment supporting high-speed SerDes and SoC IP. Circuit areas include PLLs, clocking, ADC/DAC, TX/RX analog front ends, and calibration loops. The engineer will work closely with analog circuit designers, RTL designers, and verification engineers, and will lead and participate in modeling and verification of leading-edge designs in advanced CMOS processes.

The role includes interpreting schematics, netlists, and circuit specifications to determine model behavior; defining model architecture and accuracy targets while balancing fidelity with simulation speed; writing and validating behavioral models against transistor-level simulation results; debugging simulation failures and identifying root causes in models, RTL, or testbenches; and documenting model behavior, limitations, and interfaces.

Requirements

• Hands-on experience writing behavioral models of analog circuits in SystemVerilog.
• Working knowledge of analog and mixed-signal circuit fundamentals.
• Working knowledge of the SystemVerilog UVM methodology.
• Proven skill debugging failures in simulation and waveforms.

Nice To Haves

• Familiarity with high-speed interface standards.

Responsibilities

• Read schematics, netlists, and circuit specifications to define what each model must capture.
• Develop model architecture and accuracy targets, balancing fidelity against simulation speed.
• Write behavioral SystemVerilog models of analog blocks.
• Validate models against transistor-level simulation results.
• Debug simulation failures and identify root causes in the model, RTL, or testbench.
• Document model behavior, limitations, and interfaces.
• Lead and participate in the modeling and verification of leading-edge designs in advanced CMOS processes.
• Work closely with analog circuit designers, RTL designers, and verification engineers.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed