The Senior ASIC RTL Engineer will be a key member of Cisco’s Silicon One development organization. The role collaborates closely with Front-end RTL and backend physical design teams to develop a deep understanding of chip architecture. Its primary focus is driving high-quality Design for Test (DFT) RTL and delivering robust, reliable silicon solutions that meet Cisco’s standards for performance and innovation. Cross-functional teamwork supports advanced networking silicon aligned with Cisco Silicon One’s scalable and flexible architecture.
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Job Type
Full-time
Career Level
Senior