RTL Design Engineer

Wipro • Mountain View, CA

1d

About The Position

Wipro is seeking an RTL Design Engineer to deliver ASIC/SoC designs, particularly arbitration and fabric logic for high-throughput, low-latency data transport. The role involves digital design and RTL coding, as well as setting up, maintaining, and debugging RTL-to-physical-design tools and flows, including lint, CDC, RDC, VCLP, synthesis, timing constraints, and formal equivalence verification. The engineer will work with physical design engineers to assess microarchitecture tradeoffs against performance, area, and power constraints. The posting describes a broad experience range and lists RTL coding as a mandatory skill.

Requirements

• Experience delivering successful IP or ASIC/SoC designs related to arbitration and fabric logic for high-throughput, low-latency data transport; the role-purpose criteria specify 8+ years.
• Expertise in digital design, including RTL coding in Verilog/SystemVerilog and RTL-to-physical-design tool/flow setup, maintenance, and debugging; the role-purpose criteria specify 8+ years.
• The role-purpose section lists these experience alternatives: 9+ years of related technical engineering experience; or a relevant bachelor's degree and 6+ years of technical engineering experience or internship experience; or a relevant master's degree and 4+ years of technical engineering experience or internship experience.
• Mandatory skill: RTL coding.
• Strong communication skills and ability to facilitate collaboration.

Nice To Haves

• The preferred-qualifications section lists these experience alternatives: 15+ years of technical engineering experience; or a relevant bachelor's degree and 12+ years of technical engineering experience; or a relevant master's degree and 8+ years of technical engineering experience; or a relevant doctorate and 5+ years of technical engineering experience.
• Track record of successful ASIC tape-outs in deep sub-micron technologies.
• Deep understanding of the physical-design impact of microarchitecture and ability to work with physical design engineers on performance, area, and power tradeoffs.
• Experience with complex control paths, memory hierarchies, and industry-standard interfaces such as AXI.
• 5+ years of experience designing complex control logic on Network-on-Chip ASICs.

Responsibilities

• Deliver IP or ASIC/SoC designs related to arbitration and fabric logic for high-throughput, low-latency data transport.
• Perform digital design and RTL coding in Verilog and SystemVerilog.
• Set up, maintain, and debug RTL-to-physical-design tools and flows, including lint, CDC, RDC, VCLP, synthesis, timing constraints, and formal equivalence verification.
• Work closely with physical design engineers to evaluate microarchitecture tradeoffs against performance, area, and power constraints.
• Design complex control logic for Network-on-Chip ASICs.

Benefits

• Medical and dental benefits options
• Disability insurance
• Paid time off, inclusive of sick leave
• Other paid and unpaid leave options

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed