Senior ASIC RTL Design Engineer

Cynet Systems • San Jose, CA

1d

About The Position

The Senior ASIC RTL Design Engineer drives low-power design strategies, synthesis, and timing closure for complex SoC and IP designs. The role uses industry-standard EDA tools to optimize power, performance, and area (PPA), producing efficient, reliable silicon that meets product requirements. The successful candidate is passionate about digital design, power optimization, and timing closure in advanced semiconductor technologies; is detail-oriented and analytically minded; and works collaboratively with teams across different time zones. The role also includes building test-plan documentation that accounts for interactions with other features and hardware.

Requirements

• Strong background in ASIC synthesis and static timing analysis (STA).
• Hands-on expertise with EDA tools such as Design Compiler, PrimeTime, PrimePower, Power Artists, or equivalent.
• Experience with power analysis and optimization techniques, including clock gating, multi-Vt, power gating, and multi-voltage design.
• Familiarity with UPF/CPF power-intent specification and verification.
• Solid understanding of digital design fundamentals and RTL coding in Verilog/SystemVerilog.
• Proficiency in scripting languages such as TCL, Perl, Python, or Shell for flow automation.
• Knowledge of low-power design methodologies and trade-offs.
• Experience with Verilog, SystemVerilog, C, and C++.
• Ability to automate workflows in a distributed compute environment.

Nice To Haves

• Experience with advanced process nodes such as 7nm, 5nm, or 3nm.
• Exposure to floorplanning, place-and-route, and ECO flows.
• Prior leadership, mentorship, or cross-functional collaboration experience.
• Graphics pipeline knowledge.

Responsibilities

• Develop and implement power-reduction strategies across SoC/IP designs.
• Perform synthesis and static timing analysis (STA) to achieve PPA targets.
• Analyze and optimize dynamic and leakage power using industry-standard tools.
• Collaborate with RTL design, physical design, and verification teams to meet timing and power requirements.
• Run low-power verification checks (UPF/CPF) and validate correct implementation of power intent.
• Support sign-off activities for lint, CDC, synthesis, timing, and power closure.
• Automate and streamline power and timing workflows to improve efficiency.
• Build test-plan documentation accounting for interactions with other features and hardware.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed