Ambiq is seeking a Principal RTL Engineer to own pre-tapeout quality for digital SoC modules on its MCU platforms and drive architecture, microarchitecture, and RTL development for next-generation silicon. This is a hands-on principal individual-contributor role for an engineer experienced in building and debugging complex SoCs, improving quality before tapeout, and contributing directly to production silicon. The role involves developing Verilog/SystemVerilog RTL for complex IPs and SoCs, evaluating and integrating third-party IP, and working with verification and FPGA teams on test planning and debug. The engineer will collaborate with physical design to meet timing and power targets, run and address LINT, CDC, and RDC checks, and assist with silicon bring-up and validation.
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Job Type
Full-time
Career Level
Principal