Principal SoC RTL Engineer

Ambiq Micro•Austin, TX

About The Position

Ambiq is seeking a Principal RTL Engineer to own pre-tapeout quality for digital SoC modules on its MCU platforms and drive architecture, microarchitecture, and RTL development for next-generation silicon. This is a hands-on principal individual-contributor role for an engineer experienced in building and debugging complex SoCs, improving quality before tapeout, and contributing directly to production silicon. The role involves developing Verilog/SystemVerilog RTL for complex IPs and SoCs, evaluating and integrating third-party IP, and working with verification and FPGA teams on test planning and debug. The engineer will collaborate with physical design to meet timing and power targets, run and address LINT, CDC, and RDC checks, and assist with silicon bring-up and validation.

Requirements

  • Bachelor’s degree in Electronics Engineering, Electrical Engineering, Instrumentation & Control Engineering, or a related field, plus 20 years of experience.
  • Deep and broad knowledge of current and emerging SoC design technologies.
  • Expertise in designing, implementing, and troubleshooting IPs and SoCs.
  • Ability to understand customer needs and the competitive landscape.
  • Ability to estimate impact, help plan and lead implementations, and positively affect overall output.
  • Ability to architect and guide programs across a broad range of technical areas.

Responsibilities

  • Own pre-tapeout quality for digital SoC modules on MCU platforms.
  • Explore architecture and develop microarchitecture.
  • Develop RTL for IPs and SoCs using Verilog.
  • Identify, select, and integrate third-party IP.
  • Collaborate with verification and FPGA teams on test-plan development and debug.
  • Collaborate with the physical design team to close designs against timing and power targets.
  • Assist with silicon bring-up and validation.
  • Run LINT, CDC, and RDC quality-check tools and fix or waive issues.
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