RTL Intern

quadric • Burlingame, CA

13d • $50 - $57 • Onsite

About The Position

Quadric is hiring an RTL Intern to support the SoC design team as it develops its General Purpose Neural Processing Unit (GPNPU) platform. The intern will gain hands-on experience with next-generation SoC architecture, front-end design, and integration methodologies, working alongside the hardware team and SoC architects. The work includes subsystem development, third-party IP integration, and power, performance, and area (PPA) optimization.

The internship is preferred to be based at Quadric’s downtown Burlingame, California office. Candidates should be based in the Bay Area or able to relocate for the internship period, and available to work onsite. The position is temporary and pays $50–$57 per hour, with the actual offer depending on role level, geography, relevant experience, and skills.

Requirements

• Currently pursuing a Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a related field.
• Familiarity with SoC/ASIC front-end design concepts.
• Proficiency in SystemVerilog or Verilog.
• Prepared to collaborate with architects and designers on subsystem development and integration tasks.
• Demonstrated problem-solving, debugging, and clear technical communication capabilities.
• Based in the Bay Area or able to relocate for the internship period, and available to work onsite.

Nice To Haves

• Coursework or project experience with computer architecture, low-power design, or RTL design.
• Exposure to logic synthesis, FPGA design, or performance modeling.
• Adeptness with scripting languages such as Python and using LLMs to get things done.

Responsibilities

• Help design and integrate SoC-level subsystems alongside engineers integrating third-party IP, including NoC, PCIe/UCIe interfaces, DDR, and security components.
• Contribute to documentation of SoC architecture and application requirements.
• Assist in analyzing and optimizing power, performance, and area at the SoC level.
• Gain exposure to low-power digital design techniques and timing-closure work across front-end stages.
• Work with SoC architects and designers to understand design intent and integration requirements.
• Communicate findings, blockers, and technical questions clearly to the team.

Benefits

• Hands-on experience working alongside industry experts in AI and semiconductor technology.
• Mentorship and meaningful project ownership from day one.
• Catered lunch each day in the office.
• Downtown Burlingame office location close to shops, cafes, and local amenities.
• A work culture focused on innovative disruption.

What This Job Offers

• Job Type: Full-time
• Career Level: Intern
• Education Level: No Education Listed