Intern, RTL Power Macromodeling Engineer
About The Position
Samsung’s Power & Thermal Lab is seeking an RTL-focused intern to build and validate power models used by a trace-driven power and thermal simulator for AI memory components. The lab translates RTL and trace behavior into time-indexed power models, helping address power and heat constraints in AI systems. The intern will contribute to research and product projects, work with authentic data and partners, and collaborate with hardware, software, and thermal experts. The position is based at Samsung’s San Jose headquarters and requires daily onsite presence in alignment with the company’s Flexible Work policy. The role reports to the SVP, R&D (Power & Thermal Lab).
Requirements
- Be pursuing an MS or PhD in Electrical and Computer Engineering, Computer Science, or a related field.
- Have at least one academic quarter or semester remaining.
- Have RTL design and analysis experience with Verilog, SystemVerilog, or SystemC.
- Have solid C++ or Python skills.
- Understand dynamic and leakage power in CMOS and interconnect.
- Be able to abstract circuit behavior into compact models.
- Demonstrate curiosity about power, heat, and AI hardware, and a preference for measuring rather than guessing.
- Be inclusive and adaptable to different situations and diverse global norms.
- Be an avid learner who approaches challenges with curiosity and resilience and uses data to build understanding.
- Be collaborative, build relationships, offer support humbly, and welcome others’ approaches.
- Be innovative and creative, proactively explore new ideas, and adapt quickly to change.
Nice To Haves
- Experience with power analysis tools such as PrimeTime PX, StarRC, VCS, or PowerArtist.
- Experience with architecture-level modeling tools such as McPAT, CACTI, or Wattch.
- Experience with S-parameters and SPICE.
- Experience with UCIe, high-speed I/O, or 2.5D packaging.
Responsibilities
- Develop IP-level power macromodels for AI memory components such as PHY, memory controller, interconnect, and TSV, using analytical models, lookup tables, FSMs, neural networks, and hybrid approaches.
- Extract activity-, value-, and state-dependent power features from RTL, SystemC, and C simulations.
- Support model calibration using synthesis-assisted anchors, circuit-level references, and measured data.
- Validate models against RTL and gate-level power analysis and silicon, and improve models where results disagree.
- Deliver validated models and regression checks into the trace-driven flow, collaborating with software engineers on model interfaces.
- Complete other responsibilities as assigned.
Benefits
- Medical, dental, and vision benefits.
- Relocation stipend for employees living more than 50 miles from the new office.
- Monthly housing stipend for interns signing a lease for a new place for the summer internship.
- Charitable giving match and opportunities to participate in community activities.
- On-demand emotional wellness apps and paid therapy sessions.
- Onsite café and gym, plus virtual fitness classes.
- Flexible work environment.
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What This Job Offers
Career Level
Intern
