Intern, RTL Power Macromodeling Engineer

Samsung Semiconductor•San Jose, CA

8d•Onsite

About The Position

Samsung Semiconductor’s Power & Thermal Lab is seeking an RTL-focused intern to build and validate power models used by a trace-driven power and thermal simulator for AI memory components. The work supports research and product teams across multiple projects, with mentorship and collaboration among hardware, software, and thermal experts. The intern will develop IP-level power macromodels for components such as PHY, memory controller, interconnect, and TSV. Models may use analytical methods, lookup tables, finite-state machines, neural networks, or combinations of these. The role includes extracting power features from RTL, SystemC, and C simulations; calibrating models with synthesis-assisted anchors, circuit-level references, and measured data; and validating results against RTL and gate-level power analysis and silicon. Validated models and regression checks will be incorporated into the trace-driven flow in collaboration with software engineers. The position is based at Samsung’s San Jose headquarters and requires daily onsite presence, in alignment with the company’s Flexible Work policy.

Requirements

Be pursuing an MS or PhD in Electrical and Computer Engineering, Computer Science, or a related field.
Have at least one academic quarter or semester remaining.
Have RTL design and analysis experience with Verilog, SystemVerilog, or SystemC.
Have solid C++ or Python skills.
Understand dynamic and leakage power in CMOS and interconnect.
Be able to abstract circuit behavior into compact models.

Nice To Haves

Experience with power analysis tools such as PrimeTime PX, StarRC, VCS, or PowerArtist.
Experience with architecture-level modeling tools such as McPAT, CACTI, or Wattch.
Experience with S-parameters and SPICE.
Experience with UCIe, high-speed I/O, or 2.5D packaging.

Responsibilities

Develop IP-level power macromodels for AI memory components, including PHY, memory controller, interconnect, and TSV.
Extract activity-, value-, and state-dependent power features from RTL, SystemC, and C simulations.
Support model calibration using synthesis-assisted anchors, circuit-level references, and measured data.
Validate models against RTL and gate-level power analysis and silicon, and improve models where results disagree.
Deliver validated models and regression checks into the trace-driven flow, collaborating with software engineers on model interfaces.
Complete other responsibilities as assigned.