PI) Engineer

Intel Corporation•Hillsboro, OR

1d•$141,910 - $200,340•Onsite

About The Position

Intel Corporation is the world's largest semiconductor company and a global leader in computing innovation. Our Quantum Computing Group represents Intel's bold venture into the next frontier of computing technology, leveraging our decades of semiconductor manufacturing expertise to develop silicon-based quantum processors. We're pioneering spin qubit technology in silicon quantum dots, combining cutting-edge quantum physics with Intel's unmatched manufacturing capabilities to create the world's first commercially viable quantum computers. Our collaborative approach spans Intel's research divisions and partnerships with leading academic institutions worldwide. We are seeking an exceptional Quantum Packaging Signal/Power Integrity (SI/PI) Engineer to join our pioneering quantum computing team in Oregon. In this role you will be responsible for modeling and simulation of various packaging solutions from silicon redistribution layers to IC substrates within a multidisciplinary team. You'll play a crucial role in advancing Intel's silicon quantum dot technology while contributing to the development of scalable quantum systems that will revolutionize computing.

Requirements

M.S. degree in Electrical Engineering, Physics or related field AND 3+ years of experience in SI/PI for packaging, silicon testchip, or other related hardware. OR Ph.D. degree in Electrical Engineering, Physics or related field with academic or work experience in the related areas.
SI/PI modeling, simulation, and optimization with simulation software such as SIwave, HFSS, ADS, and related.
SI/PI/thermal impact on IC substrate design choices.
Design experience with large form factor IC substrates.

Nice To Haves

1+ years of experience with testchip SI software for large-scale automation (e.g., RaptorH/X).

Responsibilities

Modeling and simulation of packaging hardware including redistribution layers (e.g., interposers, RDLs), IC substrates, and silicon testchip routing
Work closely with stakeholders to meet design requirements - requirements come from both theory and hardware teams. In some pathfinding projects, you will be asked to participate in creating requirements and novel packaging hardware.
System-level modelling and simulation; end-to-end simulations to ensure designs meet system-level requirements
Deliver and disseminate design milestones to stakeholders
Communicate designs in presentations and relevant documentation
Stay current with the latest developments in packaging technology and design techniques by attending conferences and reading papers