Distinguished Signal and Power Integrity Engineer

NVIDIA•Santa Clara, CA

About The Position

NVIDIA is seeking a Distinguished Signal and Power Integrity Engineer to provide corporate-level technical leadership for high-speed signaling across advanced semiconductor packaging, sockets, and connectors. The role sets technical direction and oversees implementation for next-generation products, ranging from ultra-mobile devices to high-performance AI and HPC platforms. The engineer will architect and deliver interconnect and packaging solutions for UCIe, HBM, DDR, PCIe, and 224G/448G SerDes, and enable technologies such as co-packaged optics, stacked die, chiplet-based architectures, and IVR solutions. The role also develops modeling and characterization flows, flow automation, and design-for-high-volume-manufacturing techniques. As a recognized subject matter expert, the engineer provides strategic counsel to senior leadership on emerging technologies, investment, and research priorities in signaling, packaging, and system integration.

Requirements

15+ years leading innovations in high-speed signal integrity, computational electromagnetics, and semiconductor assembly technologies.
MS or PhD in Electrical Engineering or equivalent, with 15+ years of industry experience.
Hands-on invention and deployment of advanced solutions, such as EMIB, UCIe, CPO, or high-density connectors.
Deep experience in electrical, computer, and packaging engineering, including deployment of solutions in products.
Demonstrated ability to manage and mentor highly skilled engineering teams, define methodologies, and deliver complex projects from research to high-volume manufacturing.

Nice To Haves

Proven track record of bringing advanced signal-integrity concepts from research to product.
Recognized pioneer in an industry-standard high-speed signaling technology.
Deep knowledge of the operational and manufacturing challenges of package substrates, PCBs, cables, and connectors.

Responsibilities

Lead development and execution of corporate-level strategies for high-speed signaling technologies across advanced semiconductor packaging, sockets, and connectors.
Oversee technical direction and implementation for next-generation products ranging from ultra-mobile to high-performance AI and HPC platforms.
Architect and deliver interconnect and packaging solutions for UCIe, HBM, DDR, PCIe, and 224G/448G SerDes.
Enable advanced packaging solutions for co-packaged optics, stacked die, chiplet-based architectures, and IVR solutions.
Develop modeling and characterization flows, flow automation, and design-for-high-volume-manufacturing techniques.
Advise senior leadership on emerging technologies, technology investment, and research priorities in signaling, packaging, and system integration.
Manage and mentor highly skilled engineering teams, define methodologies, and deliver complex projects from research through high-volume manufacturing.