Senior Signal and Power Integrity Engineer

Google•Sunnyvale, CA

16h•$163,000 - $236,000

About The Position

As a Signal Integrity/Power Integrity (SI/PI) Engineer, you will lead chip and package design, ensuring optimal SI/PI performance and system co-design from concept to production. You will collaborate with a cross-functional team including Chip Design, IP, System Design, software, and vendors to drive signal and power design implementations on chip and advanced packages. The role supports the development of TPU technology for AI/ML hardware acceleration. It focuses on SI/PI performance and system co-design for high-performance computing products using advanced packaging technologies, and includes simulation methodology development, post-silicon validation, and package design closure.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience in SI/PI design for chip/package or system PCB.
Experience with industry SIPI modeling tool chains such as HFSS, ADS, Sigrity, and Siwave.
Experience with lab bring-up, test environments, and characterization for high-speed memory and SerDes.
Experience partnering across chip architecture, physical design, static timing analysis (STA), package, and validation teams.
Experience in Python, MATLAB, or C++ to establish automated flows and data processing tools.

Nice To Haves

Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
Direct experience with silicon interposers, silicon bridges, and 3D die stacking architectures.
Deep knowledge of SI/PI analysis for high-speed interconnects (HBMx, D2D/chiplets, PCIe, SerDes) and timing budget methodologies.

Responsibilities

Lead signal integrity (SI) and power integrity (PI) analysis and optimization for High-Performance Computing (HPC) leveraging advanced 2.5D/3D packaging technologies.
Partner early in product definition to influence chip floor planning, Power Distribution Networks (PDN/power trees), netlists, and routability tradeoffs.
Evaluate high-speed interface IPs and develop next-generation memory interfaces across IO PHY, SI/PI, and physical design boundaries.
Drive post-silicon validation and qualification for NPI, balancing SI/PI performance and DFM constraints to achieve final package design closure.
Partner closely with silicon, system, and external vendor teams while developing simulation methodologies to boost modeling accuracy and efficiency.
Collaborate with Chip Design, IP, System Design, software, and vendors to drive signal and power design implementations on chip and advanced packages.