Signal Integrity Engineer III

Hewlett Packard Enterprise • Roseville, CA

2d • $109,500 - $220,500 • Onsite

About The Position

Hewlett Packard Enterprise is hiring a Signal Integrity Engineer III for its R&D Networking Platforms team in Sunnyvale, California. This onsite role contributes to signal and power integrity solutions for high-performance LAN products, supporting system-level high-speed interfaces, power distribution networks, high-precision timing, and general-purpose I/O from analysis through validation.

The engineer will develop cost-effective SI/PI solutions using analysis, simulation, design of experiments, and lab correlation. The role includes interconnect and PDN modeling, simulation, PCB stack-up and design-rule contributions, design reviews, and lab measurements correlated with simulation results. The engineer will identify and communicate risks, help resolve issues, and contribute to innovative designs and next-generation technologies.

The position works closely with hardware, layout, system, and validation engineers. The engineer will plan and manage assigned work with guidance as needed, and own analysis, documentation, and verification through completion. HPE describes a collaborative R&D environment with technical development, coaching, and knowledge-sharing opportunities. The expected U.S. base salary range is USD 109,500–220,500 annually in California; variable incentives may also be offered.

Requirements

• Bachelor’s or Master’s degree in Electrical or Electronics Engineering.
• At least 3 years of hands-on experience in product-level package or board design, SI analysis or methodology development, and lab correlation of simulation results.
• Good understanding of electromagnetics and signal integrity fundamentals, including transmission-line effects, reflections, crosstalk, insertion and return loss, ground bounce, termination techniques, I/O buffer modeling, and high-speed differential signaling.
• Working knowledge of digital and analog circuit design, including frequency-domain analysis, jitter sources, and jitter reduction techniques.
• Experience with high-speed interfaces such as Ethernet SerDes, PCIe, USB, or other SerDes-based systems.
• Experience with SI/PI simulation tools such as Synopsys HSPICE, Keysight ADS, or Ansys HFSS.
• Hands-on experience with relevant lab equipment such as VNAs, TDRs, real-time oscilloscopes, or spectrum analyzers.
• Analytical problem-solving ability to work from observed symptoms toward root cause and resolution, with support from senior engineers when needed.

Nice To Haves

• Exposure to 2-D/3-D field solvers, statistical or BER analysis, and Cadence CAD tools.
• Strong interpersonal skills and the ability to work effectively in teams while managing assigned tasks independently.
• Ability to build productive working relationships across hardware, layout, system, and validation teams; self-motivation, curiosity, and receptiveness to coaching and feedback.
• Good written and verbal communication skills, including the ability to interpret engineering drawings and technical documents, document findings, and explain SI trade-offs clearly.
• Willingness to take ownership of diverse technical challenges, learn continuously, and contribute beyond immediate responsibilities.

Responsibilities

• Support the design and validation of signal and power integrity solutions for system-level high-speed interfaces, power distribution networks, high-precision timing, and general-purpose I/O.
• Develop robust, cost-effective SI/PI solutions through analysis, simulation, design of experiments, and lab correlation.
• Perform interconnect and PDN modeling, SI/PI simulations, and analysis to help ensure designs meet performance, reliability, and industry specifications.
• Contribute to PCB stack-ups, design rules, and constraints, and participate in design reviews to ensure compliance with SI/PI best practices and standards.
• Conduct lab measurements and correlate results with simulations using lab instrumentation.
• Identify, communicate, and help resolve SI/PI risks to support high-quality, on-schedule product delivery.
• Evaluate and contribute to innovative solutions for cutting-edge designs and next-generation technologies.
• Collaborate with hardware, layout, system, and validation engineers, sharing technical knowledge and strengthening SI capability across teams.
• Plan and manage assigned work with guidance as needed, taking ownership of analysis, documentation, and verification through completion.

Benefits

• A comprehensive suite of benefits supporting physical, financial, and emotional wellbeing.
• Career development programs supporting employees’ career goals.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level