ASIC Packaging SI/PI Engineer (Hybrid)

Cisco•San Jose, CA

1d•Hybrid

About The Position

Cisco Silicon One is hiring a Signal and Power Integrity Engineer to help develop next-generation ASIC packaging for deployment across Cisco platforms. The engineer will define, design, and verify ASIC packaging and develop, document, and implement design rules for ultra-high-speed signaling while meeting product power, performance, and area goals. The role analyzes substrate signal integrity (SI) and power integrity (PI), provides feedback to the layout team, and helps optimize solutions across interposers, substrates, and PCBs. It also involves designing and documenting ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting. The engineer collaborates with system partners, vendors, and design leads to achieve power and signal integrity goals and resolve complex technical issues using advanced technology design rules. The position requires living within commuting distance of Cisco’s San Jose, California office and commuting there at least four to five days per week.

Requirements

Bachelor’s degree plus 2 years of related experience, or a master’s degree plus 0 years of related experience.
Experience with high-speed design principles, including transmission line theory, electromagnetics, scattering parameters, and impedance network analysis, specifically applied to 56G PAM4 SerDes architectures, channel modeling, and BER prediction.
Experience with pre- and post-layout SI/PI analysis.
Experience simulating with industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, or Keysight ADS, and/or with physical validation using layout reviews and design validation tools such as Cadence APD and Ansys EM flows.
Experience using lab measurements, including VNA and TDR, to validate simulation-to-measurement correlation.
Experience planning and executing SI/PI measurements and laboratory characterization, including VNA measurements, TDR, impedance profiling, insertion/return loss analysis, and full channel characterization.
Experience characterizing, validating, and debugging high-speed systems and packages using equipment such as high-bandwidth oscilloscopes, spectrum analyzers, network analyzers, and probe stations.
Must live within commuting distance of the San Jose, California office and commute to the office at least 4–5 days per week.

Nice To Haves

Experience articulating ideas and technical concepts to diverse audiences verbally and in writing.
Experience with high-bandwidth memory (HBM) or high-speed memory interface SI.
Experience with die-to-die interfaces, such as UCIe or proprietary interfaces.
Experience with advanced packaging such as CoWoS, EMIB, or interposer-based designs, including SI/PI analysis of 2.5D ASIC packaging.
Experience developing and executing test plans for high-speed interfaces, correlating measurement results with simulations, and driving root-cause analysis of SI/PI issues.
Experience analyzing and interpreting S-parameters, channel characteristics, crosstalk, reflections, impedance discontinuities, and power delivery network performance.
Experience collaborating with ASIC, package, board design, and system engineering teams to optimize end-to-end signal and power integrity.

Responsibilities

Develop, document, and implement design rules for ultra-high-speed signaling while ensuring product power, performance, and area goals are met.
Analyze substrate signal integrity and power integrity.
Provide feedback and collaborate with the layout team to develop optimal solutions across interposer, substrate, and PCB.
Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and resolve complex technical issues using advanced technology design rules.
Plan and execute SI/PI measurements and laboratory characterization, and validate simulation results against measurements.
Perform SI/PI characterization, validation, and debug of high-speed systems and packages.

Benefits

Medical, dental, and vision insurance, subject to plan eligibility rules.
401(k) plan with a Cisco matching contribution.
Paid parental leave.
Short- and long-term disability coverage.
Basic life insurance.
Paid holidays and a floating holiday for non-exempt employees.
Paid day off for an employee’s birthday.
Paid year-end holiday shutdown.
Paid personal wellness days.
Vacation time or flexible vacation time off, depending on employee classification.
Paid sick time, with limited carryforward of unused sick time.
Additional paid time away may be requested for critical or emergency family issues.
Optional paid volunteer days.
Annual bonuses for eligible non-sales employees, subject to Cisco policies.
Employees may be eligible for Cisco restricted stock unit grants, subject to continued employment and vesting terms.