Hardware ASIC Packaging SI/PI Simulation and Design Lead (Hybrid)
About The Position
Cisco Silicon One is seeking a Signal and Power Integrity Technical Lead to help develop, define, design, and verify next-generation ASIC packaging for deployment across Cisco platforms. The team works on complex, high-performance silicon ASICs and advanced IC package design, including heterogeneous system integration and 2.5D fanout technologies. The role develops and implements design rules for ultra-high-speed signaling while meeting product power, performance, and area goals. It analyzes substrate signal and power integrity and collaborates with layout teams on solutions across interposers, substrates, and PCBs. The lead designs and documents ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting, and works with system partners, vendors, and design leads to resolve technical issues. The position also defines processes, methods, and tools for complex ASIC and package development; contributes to chip architecture and high-performance ASIC design discussions; mentors engineers; influences packaging and hardware teams; and promotes design reviews, postmortems, and continuous improvement. The role is based in Cisco’s San Jose, California office, with a preference for candidates able to commute onsite four to five days per week. Fully remote candidates may also be considered. The application window is expected to close January 28, 2027.
Requirements
- Bachelor’s degree in Electrical Engineering and 8 or more years of relevant signal and power integrity experience; or a Master’s degree in Electrical Engineering and 6 or more years; or a PhD in Electrical Engineering and 3 or more years.
- Experience with high-speed design principles, including transmission line theory, electromagnetics, scattering parameters, and impedance network analysis, applied to 56G PAM4 SerDes architectures, channel modeling, and BER prediction.
- Experience with pre- and post-layout signal and power integrity simulations using industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS.
- Experience conducting detailed layout reviews and physical design validation using tools such as Cadence APD and Ansys EM flows to ensure signal performance and mitigate crosstalk.
- Experience with SPICE for circuit-level analysis, signal modeling, and performance validation.
Nice To Haves
- Ability to articulate ideas and technical concepts to diverse audiences verbally and in writing.
- Experience with high-bandwidth memory (HBM) or high-speed memory interface signal integrity.
- Experience with die-to-die interfaces such as UCIe or proprietary interfaces.
- Experience with advanced packaging, including CoWoS, EMIB, and interposer-based designs, and SI/PI analysis of 2.5D ASIC packaging.
- Experience with Vector Network Analysis.
- Experience with IBIS.
Responsibilities
- Develop, document, and implement design rules for ultra-high-speed signaling that meet product power, performance, and area goals.
- Analyze substrate signal integrity and power integrity and collaborate with the layout team on solutions across interposer, substrate, and PCB.
- Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
- Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and resolve complex technical issues using advanced technology design rules.
- Define processes, methods, and tools for complex ASIC and package development.
- Lead or participate in chip architecture discussions and the definition, architecture, and design of high-performance ASICs, including reviews of intricate IC and analog/mixed-signal circuit designs.
- Mentor and support the signal integrity team and junior engineers, and influence packaging and hardware teams to meet technical specifications and develop innovative solutions.
- Promote design reviews, postmortems, and continuous improvement across multidisciplinary engineering teams.
Benefits
- Medical insurance
- Dental insurance
- Vision insurance
- 401(k) plan with Cisco matching contribution
- Paid parental leave
- Short- and long-term disability coverage
- Basic life insurance
- Cisco restricted stock unit grants may be available, subject to eligibility and continued employment
- Paid holidays and a floating holiday for non-exempt employees
- Paid birthday day off, year-end holiday shutdown, and personal wellness days
- Paid vacation time for non-exempt employees; exempt employees participate in a flexible vacation time off program
- Paid sick time
- Additional paid time away may be requested for critical or emergency family issues
- Optional paid volunteer days
- Annual bonuses may be available for non-sales roles
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What This Job Offers
Job Type
Full-time
Career Level
Senior
