Principal Physical Design Engineer

Microsoft • Redmond, WA

12d • $142,800 - $304,200

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) supports Microsoft’s cloud infrastructure and the foundational technologies behind its online services and Azure platform. The AISiE team works to improve the planning, quality, delivery, scale, efficiency, and sustainability of Microsoft cloud hardware. Microsoft is hiring a Principal Physical Design Engineer to work on its next-generation AI SoC chip and help deliver physical-design tools, flows, and methodologies at block, sub-chip, and/or full-chip level.

The role may focus on one or more physical-design areas, including place and route, static timing analysis and timing ECOs, physical verification, formal equivalency verification, functional ECOs, global clocking construction, electromigration and IR-drop analysis, and physical-design infrastructure and IP collateral. The engineer will develop and improve physical-design execution and sign-off methodologies, contribute to design reviews, resolve design issues, and guide other engineers. The position requires Microsoft Cloud Background Check screening and eligibility to access export-controlled information.

Requirements

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and 3+ years of technical engineering experience; or a master's degree in one of these fields and 6+ years of technical engineering experience; or a bachelor's degree in one of these fields and 8+ years of technical engineering experience; or equivalent experience.
• Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
• Must provide proof of citizenship, U.S. residency, or other protected status for assessment of eligibility to access export-controlled information; citizenship will be verified with a valid passport, with other applicable documents accepted for lawful permanent residents, refugees, and asylees.

Nice To Haves

• Bachelor's or master's degree in Electrical Engineering, Computer Engineering, or a related field and 10+ years of experience.
• Experience with tapeouts of complex ASICs in leading-edge technology.
• 10+ years of block-level place-and-route experience.
• Expertise in one or more physical-design EDA tools, such as Synopsys Fusion Compiler, PrimeClosure, PrimeTime, Formality, VCLP, Star-RC, Redhawk SC, Cadence Innovus, or Siemens Calibre.
• Understanding of semiconductor design principles, methodologies, and tools.
• Proven track record of leading physical-design projects and delivering high-quality semiconductor products.
• Adequate scripting skills in TCL and Python.
• Good understanding of foundry technology files and rule decks.

Responsibilities

• Lead place-and-route convergence recipe development for block, subsystem, and sub-chip designs.
• Develop and implement methodologies and strategies to improve physical-design efficiency and performance.
• Develop and implement sign-off methodologies for static timing analysis, physical verification, functional logic equivalence, low-power verification, and electromigration and IR drop.
• Implement functional and timing ECOs while minimizing physical-design impact.
• Design and implement the global clocking scheme at SoC and sub-chip levels.
• Stay current with industry trends and emerging technologies to improve physical-design processes and methodologies.
• Install and quality-check internal and external IP collateral for use by the physical-design execution team.
• Conduct physical-design reviews, identify and resolve design issues, and provide guidance to engineers.

Benefits

• Certain roles may be eligible for benefits and other compensation; additional benefits and pay information is available through the linked Microsoft careers page.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal