Broadcom’s ASIC Products Division is seeking a Full-Chip Static Timing Analysis (STA) Engineer for its Physical Design team. The team develops custom high-performance ASICs for hyperscale cloud providers, AI companies, and networking infrastructure leaders, using advanced physical-design methodologies, leading-edge process nodes, and 2.5D/3D chiplet integration. The role is responsible for ensuring next-generation ASICs meet performance targets and timing requirements across operating conditions. It involves full-chip timing sign-off and closure, managing large-scale multi-mode multi-corner scenarios, using advanced EDA flows and AI-driven automation, and improving compute infrastructure efficiency and timing-closure speed. The position is based in San Jose, California.
Stand Out From the Crowd
Upload your resume and get instant feedback on how well it matches this job.
Job Type
Full-time
Career Level
Principal