Principal Physical Design Engineer
About The Position
Broadcom’s ASIC Products Division (APD) is seeking a Principal Physical Design Engineer to lead implementation work for next-generation high-performance networking, AI/ML accelerator, and custom cloud ASICs. The role involves complex block-level and top-level physical design across advanced deep-submicron technology nodes, from floorplanning through GDSII stream-out and signoff. The Physical Design team develops and executes implementation methodologies for large, complex custom silicon, including leading-edge foundry nodes and advanced 2.5D/3D chiplet integration. The engineer will contribute to floorplanning, synthesis, placement and routing, clock tree synthesis, timing closure, power optimization, and signoff.
Requirements
- B.S. or M.S. degree in Electrical Engineering, Computer Engineering, or a related technical field.
- 12+ years of hands-on physical design experience successfully taping out complex, high-frequency, ultra-large-scale networking or AI ASICs.
- Direct tapeout experience in TSMC advanced nodes (N7, N5, N3) or equivalent foundry processes.
- High proficiency with Cadence Innovus for place and route.
- Proficiency with Synopsys PrimeTime or Cadence Tempus for timing and static timing analysis.
- Experience with StarRC or QRC for extraction and RedHawk for IR/EM analysis.
- Experience with Siemens Calibre for DRC/LVS.
- Advanced TCL, Python, and Unix shell scripting skills for flow automation and database manipulation.
- Excellent technical leadership, problem-solving, and cross-functional communication skills.
Nice To Haves
- Strong background in high-speed clock network implementation, including H-tree, mesh, and low-power CTS.
- Experience with power-aware implementation flows, including UPF/CPF, multi-voltage domains, and clock/power gating.
Responsibilities
- Lead block-level and top-level implementation from floorplanning to GDSII stream-out using Cadence Innovus.
- Drive floorplanning, placement, clock tree synthesis, routing, and timing and power optimization on advanced technology nodes.
- Perform multi-corner, multi-mode static timing analysis and signal-integrity optimization.
- Optimize power grids and complete signoff for static and dynamic IR drop and electromigration.
Benefits
- Discretionary annual bonus.
- Competitive new-hire equity grant and annual equity awards, subject to applicable plan documents and award agreements.
- Medical, dental, and vision plans.
- 401(k) participation with company matching.
- Employee Stock Purchase Program (ESPP).
- Employee Assistance Program (EAP).
- Company-paid holidays.
- Paid sick leave and vacation time.
- Paid Family Leave and other leaves of absence in accordance with applicable laws.
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What This Job Offers
Job Type
Full-time
Career Level
Principal
