Principal Physical Design Engineer

Broadcom • San Jose, CA

6d • $143,800 - $230,000 • Onsite

About The Position

Broadcom’s ASIC Products Division is seeking a Principal Physical Design Engineer to lead physical design implementation for next-generation high-performance networking, AI/ML accelerators, and custom cloud ASICs. The role covers complex block-level and top-level implementation, including floorplanning, synthesis, place and route, clock tree synthesis, timing closure, and signoff across advanced deep-submicron technology nodes. The position is based in San Jose, California, and is full-time.

The Physical Design team develops custom high-performance silicon for cloud, AI, and networking customers. Its work includes large-scale ASIC implementation, leading-edge process nodes, 2.5D/3D chiplet integration, and development of in-house automation and methodology across EDA tools.

The engineer will lead implementation through GDSII stream-out, perform advanced-node physical design and optimization, and deliver timing, signal-integrity, power, and reliability signoff. The role requires extensive hands-on experience taping out complex, high-frequency ASICs and proficiency with physical design, analysis, extraction, verification, and automation tools.

The annual base salary range is USD 143,800 to USD 230,000. The role is eligible for a discretionary annual bonus and new-hire and annual equity awards, subject to applicable plan documents and award agreements. Broadcom also offers medical, dental, and vision plans; 401(k) participation with company matching; an Employee Stock Purchase Program; an Employee Assistance Program; company-paid holidays; paid sick leave and vacation time; and leaves consistent with applicable laws.

Requirements

• B.S. or M.S. degree in Electrical Engineering, Computer Engineering, or a related technical field.
• 12 or more years of hands-on physical design experience successfully taping out complex, high-frequency, ultra-large-scale networking or AI ASICs.
• Direct experience executing tapeouts in TSMC advanced nodes (N7, N5, N3) or equivalent foundry processes.
• High proficiency with physical design and analysis flows, including Cadence Innovus and Synopsys PrimeTime or Cadence Tempus.
• Experience with extraction and IR/EM tools such as StarRC, QRC, and RedHawk, and DRC/LVS verification using Siemens Calibre.
• Advanced TCL, Python, and Unix shell scripting skills for flow automation and database manipulation.
• Excellent technical leadership, problem-solving, and cross-functional communication skills.

Nice To Haves

• Strong background in high-speed clock network implementation, including H-tree, mesh, and low-power CTS.
• Experience with power-aware implementation flows, including UPF/CPF, multi-voltage domains, and clock or power gating.

Responsibilities

• Lead block-level and top-level implementation from floorplanning through GDSII stream-out using Cadence Innovus.
• Drive floorplanning, placement, clock tree synthesis, routing, and timing and power optimization on advanced technology nodes, including 5nm, 3nm, and 2nm.
• Perform multi-corner, multi-mode static timing analysis, signal-integrity optimization, and power-grid optimization, including static and dynamic IR-drop and electromigration signoff.
• Lead physical design implementation tasks for next-generation networking, AI/ML accelerator, and custom cloud ASICs.

Benefits

• Discretionary annual bonus eligibility.
• Competitive new-hire equity grant and annual equity awards, subject to applicable plan documents and award agreements.
• Medical, dental, and vision plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program (ESPP).
• Employee Assistance Program (EAP).
• Company-paid holidays.
• Paid sick leave and vacation time.
• Paid family leave and other leaves of absence in accordance with applicable laws.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal