Broadcom’s ASIC Products Division is seeking a Full-Chip Static Timing Analysis (STA) Engineer to ensure high-performance, next-generation ASICs meet aggressive performance targets and timing requirements across operating conditions. The role focuses on full-chip timing closure, large-scale multi-mode multi-corner analysis, and the use of next-generation EDA flows, AI-driven automation, and machine learning to improve compute infrastructure efficiency and accelerate timing closure. The Physical Design team develops advanced implementation methodologies for custom silicon, including designs on leading-edge process nodes and multi-die 2.5D/3D integrations. The position works across complex clock networks and multi-die boundaries and collaborates with RTL, Physical Design, and DFT teams to optimize power, performance, and area.
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Job Type
Full-time
Career Level
Senior