Principal Physical Design Engineer

SiTime Corporation•Santa Clara, CA

About The Position

SiTime is seeking a seasoned Principal Physical Design Engineer to lead the physical implementation and signoff of complex digital blocks and subsystems. The role owns end-to-end implementation from synthesis and floorplanning through GDSII signoff, driving power, performance, area, reliability, and schedule outcomes. As a technical leader, this engineer will shape implementation methodology and automation, resolve complex cross-functional challenges, and establish engineering best practices across multiple programs. The role also involves mentoring engineers and collaborating with architecture, design, chip-top layout, and integration teams.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field with at least 10 years of relevant experience, or a Ph.D. with at least 6 years of relevant experience.
Hands-on ASIC physical design experience and a record of driving designs from concept through successful tape-out on advanced process nodes.
Deep hands-on experience with industry-standard physical implementation and signoff tools, such as Cadence Innovus or Synopsys IC Compiler II/Fusion Compiler, together with STA, formal, physical-verification, and power-integrity platforms.
Strong scripting capability in Tcl, Perl, and/or Python for flow automation, constraint generation, and custom reporting.
Strong understanding of SDC timing constraints and concurrent MMMC optimization throughout placement, CTS, and routing.
Thorough knowledge of STA concepts, constraints, and methodologies.
Hands-on experience setting up and executing functional and timing ECOs through industry-standard ECO flows to signoff.
Strong analytical and problem-solving instincts, with the ability to communicate complex technical trade-offs clearly to peers and leadership.
Ability to drive technical alignment across cross-functional teams by communicating implementation constraints, design trade-offs, and execution risks, and influencing decisions affecting PPA, signoff, and schedule.
English proficiency sufficient to communicate, collaborate, and perform job responsibilities in a professional business environment.

Nice To Haves

12 or more years of relevant physical-design experience, including technical leadership across multiple tape-outs.
Prior experience bringing up a Place & Route (PnR) flow from scratch.
Proven experience implementing low-power methodologies, including clock gating, power gating, and multi-voltage domain design.
Experience in dynamic and static power analysis, EMIR analysis, and driving corrective actions to meet signoff targets.
Solid understanding of semiconductor process technology, device physics, and Design for Manufacturability (DFM) principles that affect physical implementation decisions.
Demonstrated ability to drive multiple chip implementations in parallel while maintaining schedule and signoff quality.

Responsibilities

Serve as the technical focal point for physical design, leading implementation and signoff reviews, mentoring engineers, and establishing reusable methodologies across multiple programs.
Lead and execute end-to-end physical design for complex digital blocks and subsystems, from synthesis through GDSII signoff, including floorplanning, power planning, place and route, clock tree synthesis, static timing analysis, formal equivalence checking, DRC, LVS, power, and EMIR.
Develop and continuously improve automated, reproducible physical-design and signoff flows to increase productivity, reduce execution risk, and ensure consistent design quality across multiple programs.
Participate in architecture and design-specification reviews, providing physical-implementation insight early to avoid downstream PPA, signoff, and schedule risks.
Architect and apply low-power implementation strategies, including clock gating, power gating, power-aware implementation, and multi-voltage design, to meet product-level power budgets.
Work with chip-top layout and integration teams to integrate digital blocks into mixed-signal, custom-layout top-level designs and resolve physical, DRC, LVS, power, clock, EMIR, and connectivity issues at block boundaries.