Senior/Principal Physical Design Engineer (remote)

Chelsea Search Group • Minneapolis, MN

2d • Remote

About The Position

The Senior/Principal Physical Design Engineer will take a key role in delivering complex, high-performance ASICs from RTL or netlist through GDSII and tapeout. The position owns critical physical implementation work, including floorplanning, placement, clock tree synthesis (CTS), routing, timing closure, and PPA optimization, using advanced technologies such as RISC-V, DDR, and SerDes.

The engineer will use Synopsys Fusion Compiler and Siemens Calibre to resolve challenging physical design problems and support successful silicon outcomes. The role involves close collaboration with a multidisciplinary ASIC engineering team and other functions, contributing technical guidance, mentoring, design reviews, and development of internal physical design capabilities.

Requirements

• 10+ years of direct industry experience with ASIC and/or SoC design.
• BSEE, MSEE, or equivalent.
• Excellent problem-solving skills and attention to detail.
• Experience with industry-standard development tools and methodologies.
• Familiarity with RISC architectures such as ARM or MIPS.
• Proficiency in Synopsys Design Compiler and other EDA tools.
• Strong background in RTL-based digital IC design using Verilog/SystemVerilog.
• Strong understanding of digital design principles.
• Proven track record of first-pass successes.
• Self-starter with the ability to assume leadership roles.
• Willingness to mentor and develop less experienced engineers.

Responsibilities

• Analyze and optimize designs to meet power, performance, and area (PPA) objectives while satisfying timing, signal integrity, reliability, and manufacturability requirements.
• Collaborate with RTL design, verification, DFT, analog/mixed-signal, packaging, and other engineering teams to ensure successful chip integration.
• Develop and optimize floorplans incorporating complex IP and high-speed interfaces, including DDR and SerDes.
• Develop, maintain, and improve physical design flows, scripts, methodologies, and automation to increase efficiency and design quality.
• Identify and resolve congestion, routing, timing, power integrity, and physical verification issues throughout implementation.
• Participate in design reviews and recommend floorplanning, physical architecture, implementation strategies, and PPA tradeoffs.
• Perform full-chip physical design implementation from synthesized netlist through GDSII, including floorplanning, power planning, placement, CTS, routing, optimization, and timing closure.
• Perform physical verification and signoff using Siemens Calibre, including DRC and LVS verification and resolution of physical design violations.
• Perform static timing analysis and drive timing closure across operating modes, process corners, and design constraints.
• Provide technical guidance and mentorship to other engineers and contribute to the development of the team's internal physical design capabilities.
• Support final design signoff and tapeout, ensuring applicable physical design and verification requirements are satisfied.
• Support integration and physical implementation of third-party and internally developed IP blocks.
• Support physical implementation and integration of RISC-V processor-based designs and subsystems, including timing, power, and physical design considerations.
• Troubleshoot complex implementation and signoff issues and drive corrective actions through resolution.
• Use Synopsys Fusion Compiler for physical implementation, optimization, and design closure.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior