Package Design Engineer

Google•Sunnyvale, CA

4h•$163,000 - $236,000

About The Position

As a Chip Package Designer on the Silicon Integration team, you will develop package substrate designs for advanced 2.5D/3.5D packaging technologies used in ML chips. You will collaborate with signal integrity/power integrity (SI/PI), thermal/mechanical, assembly, and PCB engineers to create complex, high-performance substrate designs optimized for electrical performance, reliability, and assembly. You will manage the design process from routing feasibility and test vehicle creation through product design, design reviews, artwork export, design-for-manufacturing (DFM), and final documentation. You will also help identify and incorporate advanced chip packaging technologies into Google's chip product design pipeline, supporting chip deployment in data centers and optimized power, performance, area (PPA), total cost of ownership (TCO), and system performance.

Requirements

Bachelor's degree in Mechanical Engineering, Material Engineering, Electrical Engineering, Technology, Science, a related field, or equivalent practical experience.
8 years of experience in chip package substrate design using Cadence APD or Mentor Expedition.
Experience in chip package substrate layout, design verification, DFM, and taping out for production.
Experience in design automation and scripting.

Nice To Haves

Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Experience working with cross-functional teams, including chip design, SI/PI, and PCB design teams.
Experience in 2.5D/3.5D advanced package design.
Experience in physical verification flow, including LVS, DRC, and connectivity.
Experience with CAD for creating simple mechanical drawings, such as package outline drawings (POD).
Ability to write scripts to customize elements of the Cadence or Mentor workflow.

Responsibilities

Develop physical package substrate designs for large form-factor packages used in ML high-performance computers (HPCs).
Develop and implement methodology and CAD flows for efficient substrate design and enhanced productivity.
Manage and drive co-design initiatives across chip, package, and system levels, including securing production sign-off for package designs.
Collaborate with SI/PI, thermal, and mechanical engineering teams to refine and optimize product package designs, test vehicles, and mock-up designs for product feasibility.
Define and document requirements for package substrate design and the bill of materials (BOM).
Manage design activities including routing feasibility, test vehicle creation, product designs, design reviews, artwork export, DFM, and final documentation.
Identify and incorporate advanced chip packaging technologies into the chip product design pipeline.