IC Package Design Engineer

Rivian•Palo Alto, CA

About The Position

Rivian is seeking an IC Package Design Engineer to join its ASIC team. The role leads the physical layout, modeling, and analysis of advanced semiconductor packaging solutions for high-performance integrated circuits. The engineer works with IC Design, Signal/Power Integrity, PCB Layout, Mechanical, Thermal, and Test Engineering teams, as well as substrate vendors and OSAT partners, to deliver robust, cost-effective packages from concept through volume production. The role covers package layout and advanced packaging implementations, silicon-package-board co-design, high-speed interface routing and power delivery network design, EDA-based layout and verification, and manufacturing collateral preparation. It also involves design convergence across electrical, thermal, and mechanical constraints; vendor and OSAT coordination; lab bring-up and test support; workflow automation; and exploring AI/ML-enabled engineering methods.

Requirements

B.S. or M.S. in Electrical Engineering, Computer Engineering, Materials Science, Mechanical Engineering, or a related field.
At least 3 years of hands-on experience in semiconductor package and substrate layout design, particularly for high-speed SerDes and high di/dt IC applications.
Expertise with packaging EDA tools such as Cadence Allegro APD/SiP, Cadence Virtuoso, Synopsys 3DICC, Siemens Xpedition Package Designer, or Calibre/KLayout.
Strong foundational knowledge of electromagnetics, impedance control, crosstalk minimization, substrate materials, thermal management, and mechanical reliability.
Understanding of DFM/DFT principles, JEDEC standards, DRC/LVS signoff flows, and reliability qualification processes.

Nice To Haves

At least 5 years of relevant hands-on semiconductor package and substrate layout design experience.
Hands-on experience with heterogeneous integration, chiplet architectures, silicon interposers, and 2.5D/3D IC packaging technologies.
A strong track record of working directly with top-tier OSATs, substrate manufacturers, and foundry packaging teams.
Experience writing Python, Tcl, Perl, or MATLAB scripts for workflow automation, or leveraging modern AI/ML applications in engineering workflows.

Responsibilities

Own physical package layout execution, including die placement, bump assignment, floor planning, ball map optimization, bump-to-ball fan-out planning, stack-up definition, and layer planning.
Design and develop advanced IC packaging solutions, including FCBGA, SiP, and 2.5D/3D IC architectures such as interposers, CoWoS, EMIB, and FOWLP.
Collaborate with silicon and system teams on die/package/PCB co-design, floor planning, ball maps, and interposer routing.
Define and route high-speed interfaces such as DDR, PCIe, and SerDes, and design robust power delivery networks for high di/dt requirements.
Create, manage, and validate package layouts using industry-standard EDA tools.
Perform DRC, LVS, netlist verification, and DFM/DFT reviews.
Generate and validate manufacturing collateral, including Gerbers, ODB++, and BOMs, for tapeout and manufacturing release.
Coordinate with SI/PI, thermal, and mechanical engineering teams to resolve power, signal integrity, thermal, and mechanical reliability constraints.
Work with foundries, substrate vendors, and OSAT partners to evaluate feasibility, select packaging materials and design rules, maximize manufacturing yield, and execute tapeouts.
Support lab bring-up, debugging, and silicon validation of packaged devices, and collaborate with test engineering on probe card and test socket interface design.
Develop scripting tools using languages such as Python, Tcl, Perl, or MATLAB to automate layout workflows and improve design efficiency.
Explore and promote AI/ML-enabled methods, including predictive analytics, layout optimization, and automated rule checks.