Principal IC Package Design Engineer

Ethernovia•San Jose, CA

About The Position

Ethernovia is seeking a Principal IC Package Design Engineer to lead the architecture, design, and execution of advanced packaging solutions for next-generation Ethernet switches and PHYs. The role covers the package lifecycle from early feasibility and architectural definition through detailed layout, signal and power integrity co-design, thermal management, and release to mass production. It combines deep expertise in advanced packaging technologies, including Flip-Chip BGA and high-density substrates, with cross-functional leadership involving Silicon Design, Systems/PCB, Reliability, and external OSAT vendors. The engineer will define package concepts and substrate stack-ups, design complex high-speed layouts, partner with SI/PI and thermal engineers, and manage substrate design rules, routing, and manufacturing constraints. The role also leads technical engagement with substrate suppliers and OSATs, supports manufacturing and assembly issue resolution during NPI and production ramp, and connects IC design and system/PCB teams for chip-package-board co-design. The engineer is expected to track emerging packaging technologies and inform Ethernovia’s long-term hardware roadmap. Ethernovia develops Ethernet-based networking technology for software-defined and autonomous vehicles, robotics, and other intelligent machines. The company offers competitive compensation, pre-IPO stock options, and medical, dental, and vision insurance. The annual U.S. base salary range is $200,000–$265,000, with actual compensation depending on factors including location, qualifications, experience, skills, and internal equity.

Requirements

Bachelor’s degree in Electrical Engineering, Materials Science, Mechanical Engineering, or a related field.
10+ years of direct experience in IC package design and architecture.
Track record delivering high-volume, complex Flip-Chip BGA (FCBGA), System-in-Package (SiP), and multi-chip module (MCM) designs.
Expert proficiency with package design tools such as Cadence Allegro Package Designer (APD), SiP Layout, or Synopsys 3DIC Compiler.
Strong understanding of electromagnetic theory, transmission lines, crosstalk, and power delivery network concepts.
Deep understanding of substrate fabrication processes, assembly-line limits, and automotive-grade reliability standards, including AEC-Q100 guidelines.
Strong problem-solving skills and a data-driven approach to architectural trade-offs such as performance, cost, and yield.
Excellent communication skills, including the ability to explain complex packaging constraints to cross-functional executives and external partners.

Nice To Haves

Experience in high-speed networking, automotive electronics, or high-performance computing.
Familiarity with signal and power integrity extraction tools such as Ansys HFSS/Q3D or Cadence Clarity.

Responsibilities

Lead package concept and architecture definition, including substrate stack-ups, bump and ball maps, and pinouts, balancing cost, electrical performance, and thermal constraints.
Design complex, high-speed, multilayer packages such as FCBGA, FCCSP, and SiP using industry-standard EDA tools.
Collaborate with Signal/Power Integrity and Thermal engineers to meet SerDes, power delivery network, and thermal dissipation targets.
Define substrate design rules and manage substrate layout, routing optimization, and design-for-manufacturing and assembly constraints.
Lead technical engagements with substrate suppliers and OSATs, evaluate vendor capabilities, negotiate design rules, and resolve manufacturing and assembly issues during NPI and production ramp.
Coordinate chip-package-board co-design between Silicon IC Design and System/PCB teams.
Monitor semiconductor packaging developments, including advanced organic and glass substrates and co-packaged optics, and contribute to the company’s long-term hardware roadmap.