Principal IC Package Design Engineer

Ethernovia, Inc.•San Jose, CA

7h•$200,000 - $265,000

About The Position

Ethernovia is seeking a Principal IC Package Design Engineer to lead the architecture, design, and execution of advanced packaging solutions for next-generation Ethernet switches and PHYs. The role covers the package lifecycle, from early feasibility and architectural definition through detailed layout, signal and power integrity co-design, thermal management, and release for mass production. It combines advanced packaging expertise with cross-functional leadership across silicon design, systems and PCB, reliability, and external OSAT vendors. The engineer will develop package architectures and execute high-speed, multilayer package layouts, partnering with signal/power integrity and thermal engineers to meet electrical, power-delivery, and thermal targets. The role also manages substrate integration and vendor engagements, supports NPI and production ramp, and connects silicon IC design with system and PCB teams. The position contributes to the company’s longer-term hardware roadmap by tracking emerging packaging technologies. Ethernovia describes itself as developing Ethernet-based networking for software-defined and autonomous vehicles, robotics, and other intelligent machines. The company offers a competitive base salary, pre-IPO stock options, medical, dental, and vision insurance, and flexible hours. The annual U.S. base salary range is $200,000–$265,000; actual offers vary based on factors including location, qualifications, experience, skills, and internal equity.

Requirements

B.S. in Electrical Engineering, Materials Science, Mechanical Engineering, or a related field.
At least 10 years of direct experience in IC package design and architecture, ideally in high-speed networking, automotive electronics, or HPC.
Demonstrated delivery of high-volume, complex FCBGA, SiP, and MCM designs.
Expert proficiency with package design tools such as Cadence Allegro Package Designer (APD), SiP Layout, or Synopsys 3DIC Compiler.
Strong understanding of electromagnetic theory, transmission lines, crosstalk, and power delivery network concepts.
Deep understanding of substrate fabrication processes, assembly line limits, and automotive-grade reliability standards such as AEC-Q100 guidelines.
Strong problem-solving skills and a data-driven approach to architectural trade-offs, including performance, cost, and yield.
Excellent communication skills, including the ability to explain complex packaging constraints to cross-functional executives and external partners.

Nice To Haves

Familiarity with signal and power integrity extraction tools such as Ansys HFSS/Q3D or Cadence Clarity.
Experience in high-speed networking, automotive electronics, or high-performance computing.
Knowledge of advanced organic substrates, glass substrates, or co-packaged optics.

Responsibilities

Lead package concept definition, including substrate stack-ups, bump and ball maps, and pinouts, balancing system cost, electrical performance, and thermal constraints.
Execute complex, high-speed, multilayer package layouts for FCBGA, FCCSP, and SiP using industry-standard EDA tools.
Collaborate with signal/power integrity and thermal engineers on package designs for high-speed SerDes, power delivery networks, and thermal dissipation requirements.
Define substrate design rules and manage substrate layout, routing optimization, and manufacturing constraints, including DFM/DFA.
Lead technical engagements with substrate suppliers and OSATs; evaluate vendor capabilities, negotiate design rules, and resolve manufacturing and assembly issues during NPI and production ramp.
Coordinate silicon IC design and system/PCB teams to support chip-package-board co-design and optimization.
Track emerging semiconductor packaging technologies and contribute to Ethernovia’s long-term hardware roadmap.