Principal Digital IC Design Engineer

Chelsea Search Group•Minneapolis, MN

About The Position

Design and deliver complex custom ASICs from concept through silicon. This is a hands-on role focused on digital design across the full ASIC/SoC development flow, collaborating with architecture, verification, physical design, applications, and business teams to translate technical requirements into high-performance silicon while optimizing power, performance, and area (PPA). The role also contributes to evaluating customer requirements, developing technical approaches and effort estimates for new opportunities, and improving internal design methodologies and processes. Additional experience in radiation-hardened design, analog/mixed-signal circuits, EDA methodologies, or standard-cell library development can be applied and expanded.

Requirements

  • BSEE, MSEE, or equivalent.
  • 10+ years of direct industry experience with ASIC and/or SoC design.
  • Proficiency with Synopsys Design Compiler and other EDA tools.
  • Strong understanding of digital design principles.
  • Familiarity with RISC architectures such as ARM or MIPS.
  • Strong background in RTL-based digital IC design using Verilog/SystemVerilog.
  • Proven track record of first-pass successes.
  • Proficiency with UNIX/Linux, including shell scripting, text utilities such as sed, awk, and grep, and using Modules.
  • Experience with high-level programming such as C/C++ and PERL, Python, or TCL scripting.
  • Proficiency with Windows applications including Word, Excel, PowerPoint, Visio, Project, and PDF conversion.
  • Experience with industry-standard development tools and methodologies.
  • Excellent problem-solving skills and attention to detail.
  • Ability to work well in a diverse team environment.
  • Self-starter with the ability to assume leadership roles.
  • Willingness to mentor junior engineers.

Nice To Haves

  • Experience in radiation-hardened design.
  • Experience with analog/mixed-signal circuits.
  • Experience with EDA methodologies.
  • Experience with standard-cell library development.

Responsibilities

  • Lead the architectural design of ASICs based on high-level requirements and block diagrams.
  • Collaborate with system architects to define chip functionality, interfaces, and performance targets.
  • Develop detailed specifications for chip components.
  • Create RTL designs using Synopsys Design Compiler and optimize RTL for area, power, and performance.
  • Implement and verify complex digital blocks.
  • Develop timing constraints for the entire chip and work with physical design teams to support successful place-and-route.
  • Constrain and verify RISC processors within the chip, and optimize processor performance and power efficiency.
  • Collaborate with physical design teams on floorplanning, placement, and routing, and address design-closure issues.
  • Work with verification engineers to ensure functional correctness and assist in creating testbenches and verifying chip functionality.
  • Evaluate customer requirements and develop technical approaches and effort estimates for new opportunities.
  • Influence improvements to internal design methodologies and processes.
  • Use modern revision-control tools and best practices in a collaborative, multi-site design community.
  • Mentor junior engineers and assume leadership roles as needed.
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