Digital IC Design Verification Engineer
About The Position
Specs Inc. is a wholly-owned subsidiary of Snap Inc. dedicated to making computing more human. The company develops Specs, advanced eyewear that seamlessly integrates digital experiences into the physical world. Specs feature see-through lenses that place digital objects directly into three-dimensional space, powered by Snap OS, a proprietary, context-aware operating system designed for natural interaction with your hands and voice. Specs Inc. also provides Lens Studio, a full suite of advanced developer tools that powers immersive augmented reality experiences across Specs, Snapchat, and other services. We’re looking for a Custom IC Layout Engineer to join the MicroDisplay Electronics at SPECS.
Requirements
- Strong working knowledge of custom (transistor-level) layout, including matching techniques
- Strong working knowledge of Cadence Virtuoso (Layout and Schematic) tool suite
- Strong working knowledge of Mentor/Siemens Calibre tool suite (DRC, LVS, Extraction)
- Scripting and automation, such as TCL, SKILL, Perl, Python and Shell scripts in Linux environment
- Experience and capability to execute project tape out verification including DRC, ERC and LVS
- Extensive understanding of signal integrity, reliability, layout effects (EM, IR drop) and other considerations
- Knowledge of tool flows and techniques for achieving foundry DFM requirements
- Track record of prior detailed design and custom layout experience of various types of designs such as SRAM, level shifters, IO design (ESD, latch-up), PLLs, Bandgaps, ADCs, DACs and amplifiers.
- BSEE or relevant years of experience
- 5+ years in directly applicable work performing custom layout
Nice To Haves
- Detailed understanding of 22nm and below CMOS foundry design node rules and requirements.
- Experience with both Analog and Memory layouts
- Excellent technical, documentation and verbal skills working with engineering and management teams
- Knowledge of ASIC IC test and characterization
- Understanding of digital design and place and route principles
Responsibilities
- Work as part of a multi-disciplinary team designing display ICs for AR
- Work closely with digital and analog logic, circuit and physical design engineers & other custom layout engineers
- Perform cell and block layout of Analog and Mixed-Signal circuit functions, meeting design rules and performance
- Craft reusable scripts and methodologies that help automate design flow, repeatability and efficiency
- Implement circuit layout strategies for optimal area, performance and power goals.
- Support IC floor planning and place & route of full chip digital designs with digital and analog IP
- Provides schedule, and cost inputs to program management
- Create and present design documentation for internal design reviews
- Execute parasitic extraction of circuit layout and iterate design improvements
Benefits
- paid parental leave
- comprehensive medical coverage
- emotional and mental health support programs
- compensation packages that let you share in Snap’s long-term success
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What This Job Offers
Job Type
Full-time
Career Level
Senior
Education Level
Associate degree
