MTS Package engineer - ASIC package design, logic integration and design rules
About The Position
Micron Technology is hiring an MTS Package Engineer for its Package Pathfinding and Architecture organization, which works across silicon, packaging, systems, and customer needs to develop packaging technologies for complex memory systems and next-generation platforms. The role partners with system architects and engineering teams to define package architecture, connectivity, and electrical requirements, and supports ASIC/package co-design and system-in-package integration. The engineer develops and verifies package schematics, block diagrams, and netlists; evaluates electrical performance, manufacturability, reliability, and system requirements; and collaborates with package design and signal- and power-integrity teams on implementation. The role also supports memory, ASIC, and controller integration, evolving high-speed interfaces and protocol enablement, design-rule roadmaps, validation and product bring-up, reliability failure analysis, and improvements to integration methods, verification, and automation. Technical leadership, documentation, mentoring, and interest in developing Agentic AI workflows are also part of the role.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or a related field, with 10 or more years of experience.
- Proven experience in hardware design and development, including block diagrams, schematics, and electrical requirements.
- Strong understanding of system architecture and ability to collaborate with System Level Architects.
- Familiarity with NAND flash memory technology, controller design, and storage system behavior.
- Proficiency with EDA schematic and simulation tools such as Cadence Allegro System Capture, Synopsys Design Compiler, Mentor Graphics PADS, Altium Designer, and OrCAD.
- Experience with ASIC architecture in storage products such as SSD, eMMC, UFS, or USB, and with high-speed serial and parallel interfaces such as PCIe, MIPI, DDR, LPDDR, and ONFI.
Nice To Haves
- Experience in semiconductor package design, architecture, or integration.
- Experience with schematics, netlists, connectivity definition, and verification.
- Understanding of ASIC/package and System-in-Package integration.
- Knowledge of signal integrity, power integrity, and package electrical design.
- Familiarity with memory and high-speed interfaces such as DDR/LPDDR, ONFI, UFS, and PCIe.
- Experience with EDA tools for schematic capture, package design, or connectivity verification.
- Familiarity with advanced packaging, substrate technologies, and assembly processes.
- Strong cross-functional technical leadership and problem-solving skills.
Responsibilities
- Partner with System Architects and engineering teams to define package architecture, connectivity, and electrical requirements.
- Develop block diagrams, schematics, and logical connectivity for system-in-package designs.
- Create and verify package netlists using schematic and automation-based design flows.
- Support ASIC/package co-design, including pad/bump maps, connectivity, and package integration.
- Evaluate package designs for electrical performance, manufacturability, reliability, and system requirements.
- Collaborate with Package Design and SI/PI teams to support physical and electrical implementation.
- Support integration of memory, ASICs/controllers, and other devices within complex package architectures.
- Support new and evolving interfaces such as LPDDR/DDR, ONFI, UFS, PCIe, and other high-speed protocols.
- Lead technical reviews and resolve package connectivity and integration issues through design, validation, and product bring-up.
- Develop technical documentation and provide technical guidance and mentoring to engineering teams.
- Work with TPM and factory teams to develop a design-rules roadmap for packaging across memory and ASIC roadmaps.
- Support improvements in package integration, design methodology, verification, and automation.
- Support new protocol enablement, including SCA (Separate Command Address), ONFI, UFS, and PCIe, and capability bring-up.
- Support root-cause debugging of reliability-test failures through electrical failure analysis (EFA) and physical failure analysis (PFA), and pursue resolution and improvements with multifunctional teams.
- Develop or contribute to Agentic AI workflows in current or future processes.
Benefits
- Choice of medical, dental, and vision plans.
- Programs to protect income in case of illness or injury.
- Paid family leave.
- Paid time off.
- Paid holidays.
- Additional compensation may include bonuses and equity.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
