Staff Package Design Engineer

Renesas Electronics•Tempe, AZ

1d•Onsite

About The Position

The Staff Package Design Engineer works at the intersection of IC design, advanced package development, and system-level implementation. As a Staff-level contributor, this person serves as the technical focal point for architecture and physical design of next-generation, high-performance semiconductor packages, including 2.5D/3D heterogeneous integration, chiplet-based architectures, high-density interposers, and advanced substrate technologies. The role requires expertise in advanced packaging R&D and cross-domain co-design, including defining methods and procedures for complex, multi-die integration assignments. The engineer leads alignment with global silicon design, signal integrity/power integrity (SI/PI), thermal, and product engineering teams, and drives creation of new packaging design rules and methodologies. Renesas is an embedded semiconductor solution provider with a global team of more than 21,000 engineers and problem solvers in over 30 countries. Its technologies serve Automotive, Industrial, Infrastructure, and IoT markets. The company describes its culture as Transparent, Agile, Global, Innovative, and Entrepreneurial. A competitive benefits package is offered alongside salary; further information is provided during the hiring process. Renesas is an equal opportunity and affirmative action employer. The role is not available for remote work. The position is regular (permanent).

Requirements

At least 8 years of related experience with a bachelor's degree, or at least 6 years with a master's degree; alternatively, at least 5 years of intensive R&D experience in advanced 2.5D/3D heterogeneous packaging involving bridge/interposer architectures, with demonstrated experience establishing new design rules and authoring engineering BKMs.
Strong background in advanced substrate-based packages, flip-chip layout, multi-die/chiplet-based architectures, thermal mitigation, and high-density routing.
High proficiency with industry-standard package design tools, specifically Siemens/Mentor Xpedition (Layout / Substrate Integrator), Valor NPI, and/or Cadence Allegro Package Designer / SiP Layout.
Working understanding of SI/PI fundamentals, impedance control, and crosstalk mitigation, and ability to balance these constraints against pin budgets and platform integration requirements.
Strong communication and technical documentation skills.
Proven ability to lead multidisciplinary test vehicle or product design meetings and secure tooling/supplier approvals independently.
Bachelor's or master's degree in Mechanical Engineering, Electrical Engineering, Microelectronics, Materials Science, or a related technical discipline.

Responsibilities

Lead package layout architecture and physical design for next-generation heterogeneous integration, including 2.5D/3D chiplet packaging, high-density interposers, bridge technologies, RDL, and advanced FCBGA solutions.
Define, establish, and optimize package design rules and assembly Best Known Methods (BKMs).
Partner with foundries, substrate vendors, and OSATs to evaluate and validate advanced packaging capabilities, DRCs, and manufacturing limits.
Act as the primary package architecture lead across SI/PI, thermal, tooling, and platform integration teams.
Lead design reviews to establish project scope, align stakeholder requirements, and balance pin budgets against electrical and mechanical trade-offs.
Manage package design cycles, including footprint assignment, stack-up structures, high-speed escape routing, power/ground distribution, and generation of manufacturing release outputs such as Gerber/drill data, bump maps, and assembly drawings.
Provide technical mentorship to junior and intermediate package design engineers.
Establish standardized CAD workflows, layout techniques, and technical training to promote consistent execution across the department.