Package Design Engineer – Principal Engineer

Qualcomm • San Diego, CA

4d • $210,000 - $315,000

About The Position

Qualcomm Technologies, Inc. is seeking a Principal Engineer / Director of Engineering to lead and develop the CHS Datacenter package design team. The role sets and executes end-to-end package design strategy for next-generation high-performance compute products, from concept, feasibility, and technology selection through design release, qualification, production ramp, and sustaining support. It includes building a high-performing team and delivering differentiated package solutions using advanced 2.5D and 3D integration technologies.

The position combines strategic leadership with hands-on technical oversight of multi-chiplet packaging, silicon interposer and bridge architectures, high-density interconnects, package physical design, high-speed I/O, signal and power integrity, and thermal-mechanical co-design. The leader works across silicon design, platform architecture, manufacturing, supply chain, and external technology partners to define package technology roadmaps and meet performance, power, reliability, yield, schedule, and cost objectives. The role also establishes scalable design methodology, infrastructure, signoff, verification, and release processes, and represents package engineering in program and executive reviews.

Requirements

• Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or a related field and 8+ years of System/Package Design/Technology Engineering or related work experience; or a master's degree in one of these fields and 7+ years; or a Ph.D. in one of these fields and 6+ years.
• Proven leadership of advanced package design or package architecture teams, including hiring, mentoring, performance development, workload planning, and building technical leadership capacity.
• Deep expertise in advanced semiconductor packaging for AI, HPC, server, or networking products, including multi-chiplet 2.5D/3D integration, HBM, silicon interposers, silicon bridges, Flip-Chip BGA, and high-density substrates.
• Strong system-level understanding of chip-package-board interactions and ability to translate product goals into executable package requirements.
• Expertise in package architecture and physical design, including die and HBM placement, bump planning, package pinout, routing topology, layer-stack optimization, power/ground planning, board escape, and manufacturability.
• Strong competency in package SI/PI and electromagnetic design for high-speed I/O and power delivery, including transmission-line behavior, crosstalk, return paths, S-parameters, RLGC models, PDN impedance, and decoupling strategy.
• Working knowledge of package thermal-mechanical design and reliability, including warpage, stress, material interactions, assembly risks, thermal interfaces, failure mechanisms, and qualification requirements.
• Expertise with Cadence APD/SiP and/or Siemens Xpedition Package Designer, including Constraint Manager, design-rule definition, in-line checking, DRC, DFM, ERC, and package release flows.
• Ability to interpret and guide analyses using package extraction and SI/PI tools such as XtractIM, PowerSI, HFSS, Q3D, or equivalent tools.
• Ability to define and deploy design methodologies, automation, verification strategies, review checklists, metrics, and continuous-improvement initiatives.
• Excellent executive communication, cross-functional influence, technical decision-making, and conflict-resolution skills.
• Strong partnership skills with foundries, OSATs, substrate suppliers, EDA vendors, and internal product organizations, including experience resolving issues across organizational boundaries.

Nice To Haves

• Master's degree or Ph.D. in Electrical Engineering, Mechanical Engineering, Materials Science, Chemical Engineering, or a related field, with 15+ years of relevant semiconductor and packaging experience; equivalent industry experience may be considered.
• Demonstrated record of leading and developing an advanced package engineering organization or substantial technical team supporting multiple complex products.
• Experience owning 2.5D/3D multi-die package architecture and execution for high-power AI, HPC, server, accelerator, or networking products from concept through production.
• Direct experience integrating compute SoCs or chiplets with HBM and delivering silicon-interposer, silicon-bridge, or equivalent high-density package solutions.
• Experience defining package technology roadmaps and influencing silicon floorplan, bump architecture, die-to-die topology, substrate/interposer architecture, board interfaces, thermal solution, and product cost.
• Proven understanding of HBM, UCIe or other die-to-die interfaces, PCIe, DDR, and high-speed SerDes, including package-level SI/PI and layout implications.
• Experience with advanced substrate manufacturing, materials, stackups, design rules, assembly processes, package qualification, yield learning, and package failure mechanisms.
• Experience working directly with leading foundries, OSATs, substrate suppliers, and EDA partners to evaluate, develop, qualify, and ramp new package technologies.
• Experience with Calibre or equivalent physical-verification tools and establishing package signoff criteria for DRC, DFM, ERC, SI/PI, thermal-mechanical, and release reviews.
• Demonstrated innovation through package architecture, methodology, automation, patents, publications, or industry-standard engagement.
• Proven ability to operate effectively in a matrixed global organization and lead through influence across silicon, package, board, system, manufacturing, and supplier teams.

Responsibilities

• Provide technical and organizational leadership for the CHS Datacenter package design team, including recruiting, developing, mentoring, and retaining team members.
• Own advanced package architecture and design strategy for Datacenter and HPC products from feasibility and technology selection through production and sustaining support.
• Select and optimize architectures for advanced multi-die packages, including 2.5D/3D integration, HBM, silicon interposers and bridges, and high-density organic substrates.
• Lead chip-package-board co-design across silicon floorplan, die partitioning, bump maps, die and HBM placement, package pinout, routing, power delivery, package size, board escape, and system constraints.
• Partner with silicon design, physical design, platform architecture, SI/PI, thermal, mechanical, product engineering, manufacturing, and supply-chain teams to balance product objectives.
• Guide package and SiP physical design, layout optimization, design verification, tapeout, design reviews, and release readiness.
• Define package-level electrical requirements for HBM, UCIe and other die-to-die links, PCIe, DDR, and high-speed SerDes, and ensure designs meet SI/PI targets.
• Drive thermal-mechanical co-design and reliability risk mitigation for high-power, large-body packages.
• Establish and improve package design methodology, CAD infrastructure, automation, DRC/DFM/ERC signoff, data management, design reviews, and release processes.
• Lead technical engagement with foundries, OSATs, substrate suppliers, EDA vendors, and technology partners on design rules, new capabilities, issue resolution, qualification, production ramp, and yield improvement.
• Develop package technology and capability roadmaps aligned with Datacenter product plans; identify gaps and risks and recommend mitigation plans.
• Build a culture of technical excellence, collaboration, accountability, and innovation; coach senior engineers and develop successors and technical leads.
• Represent package engineering in program and executive reviews, communicating tradeoffs, risks, resource needs, dependencies, and closure plans.

Benefits

• Competitive annual discretionary bonus program.
• Opportunity for annual RSU grants, except for employees on sales-incentive plans.
• Competitive benefits package designed to support employees at work, at home, and at play.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal