Package Design Engineer - Staff

Qualcomm•San Diego, CA
•$160,200 - $240,200

About The Position

Qualcomm Technologies, Inc.’s Data Center team is developing high-performance, energy-efficient server solutions for data center applications. The Staff Package Design Engineer will lead advanced package selection, new-generation product package structure, and configuration optimization. The role covers physical design and layout of packages and systems-in-package (SiP), optimization, design verification, and tape-out. The engineer will collaborate with multifunctional teams to achieve mechanical, electrical, and thermal performance goals across chip types, and will coordinate feasibility analysis, design, and selection for new product packages and SiP solutions. The position also develops design-verification and automation strategies, improves package design and release flows, explores CAD tools and workflows, and partners with product-design teams to optimize chip floorplans, bump placement, and package size.

Requirements

  • Proficiency in Cadence APD and SiP and/or Siemens Xpedition Package Designer (xPD).
  • Familiarity with using Constraint Manager in package-design tools to set up DFM and electrical rules.
  • Basic knowledge of signal integrity for high-speed I/O interfaces, transmission-line theory, and electromagnetic-field theory.
  • Knowledge of IC packaging structures and chip-package and package-board interactions.
  • Fundamental knowledge or proven experience in the listed package-design skills and engineering disciplines.

Nice To Haves

  • Experience with in-line DRC checking, DFM verification, and Electrical Rule Checking (ERC).
  • Master’s degree in electrical engineering, mechanical engineering, material science, or a related field, with 5 or more years of experience.
  • Proven fundamentals in electrical, material, thermal, or mechanical engineering.
  • Familiarity with sophisticated package configurations and assembly/substrate technologies, such as flip-chip BGA and 2.5D/3D interposers.
  • Experience in package design and proficiency with Cadence Allegro platform tools, including PCB Editor and Advanced Package Designer (APD/SiP).
  • Basic understanding of SI/PI tools such as XtractIM, PowerSI, HFSS, and Q3D; package-model extraction; S-parameters; and RLGC models.
  • Basic knowledge of substrate manufacturing processes, structures, design rules, and material properties.
  • Understanding of high-speed interfaces, including DDR, PCIe, and UCIE.
  • Experience with Calibre and package design reviews.
  • Knowledge of high-speed layout constraints, including crosstalk mitigation and differential pairs.
  • Solid understanding of design-rule checking and design for manufacturing.
  • Basic knowledge of electronic packaging processes and typical failure modes.

Responsibilities

  • Own and drive advanced package selection, new-generation product package structures, and configuration optimization.
  • Perform package and SiP physical design and layout, optimization, design verification, and tape-out.
  • Collaborate with multifunctional teams to optimize mechanical, electrical, and thermal performance for different types of chips.
  • Implement physical design of packages and modules for SoCs.
  • Coordinate with multifunctional Qualcomm groups on new-product package and SiP feasibility analysis, design, and selection.
  • Define and develop design-verification and automation strategies to strengthen and streamline package design and release flows.
  • Work across functions to optimize package pinout.
  • Ensure package designs are optimized for signal-integrity and power-integrity requirements.
  • Drive package-design methodology, innovation, and efficiency improvements with vendors and developers, including feature development and bug resolution.
  • Explore, evaluate, and develop CAD tools, design methods, and verification flows.
  • Partner with the BU PD team to optimize chip floorplans and bump placement and reduce package size.

Benefits

  • Competitive annual discretionary bonus program.
  • Opportunity for annual RSU grants, except for employees on sales-incentive plans.
  • Competitive benefits package.
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