Memory Design Engineer

Intel•Austin, TX

1d•Hybrid

About The Position

Intel's Corporate Memory Organization (CMO), within the Design Technology Platform (DTP), develops memory compilers on Intel's leading-edge process technologies. The organization architects, designs, and delivers high-performance, energy-efficient embedded memory IP to improve silicon performance, optimize density, and maximize manufacturing yield across Intel products and Intel Foundry platforms. As a Circuit Design Engineer in CMO, you will architect, design, and deliver SRAM compilers for high-density (HD) and high-performance (HP) profiles. You will collaborate with Intel’s Technology Development (TD) group on Design and Technology Co-Optimization (DTCO) to co-define silicon process and physical layout rules. This is an entry-level position, with compensation determined accordingly. The position is not eligible for Intel immigration sponsorship.

Requirements

Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
At least 6 months of experience in Electrical Engineering, Computer Engineering, or a related field.
At least 6 months of experience with scripting, such as Perl, Tcl, or Python.
Experience with SRAM operations.
Knowledge of transistor-level operation, such as through VLSI coursework.
Knowledge of design challenges under process variations and low-power circuit techniques.
Logical thinking, analytical, and problem-solving skills.
Verbal and written communication skills.
Interpersonal skills.
Multitasking and prioritization skills.

Responsibilities

Provide industry-competitive SRAM design solutions to meet challenging memory design specifications for various product segments.
Design, validate, and characterize Memory Compilers.
Develop Memory Compiler design flows and methodologies.
Collaborate with Intel’s Technology Development group on Design and Technology Co-Optimization to co-define silicon process and physical layout rules.
Interface with customers.