Memory Design Engineer

Intel Corporation•Austin, TX

3d•$91,150 - $172,860•Hybrid

About The Position

Intel's Corporate Memory Organization (CMO), within its Design Technology Platform, develops memory compilers for Intel process technologies. The organization architects, designs, and delivers high-performance, energy-efficient embedded memory IP intended to maximize silicon performance, optimize density, and improve manufacturing yield across Intel products and Intel Foundry platforms. As a Circuit Design Engineer in CMO, you will architect, design, and deliver SRAM compilers for high-density and high-performance profiles. You will also collaborate with Intel’s Technology Development group on Design and Technology Co-Optimization to co-define silicon process and physical layout rules. This is an entry-level position. The position is based in Austin, Texas, and uses a hybrid work model, with time split between the assigned Intel site and off-site work. The role is not eligible for Intel immigration sponsorship.

Requirements

Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
At least 6 months of experience in Electrical Engineering, Computer Engineering, or a related field.
At least 6 months of scripting experience using Perl, Tcl, Python, or similar tools.
At least 6 months of experience with SRAM operations.
At least 6 months of experience with transistor-level operation, such as VLSI coursework, including design challenges under process variations and low-power circuit techniques.
Logical thinking, analytical and problem-solving skills.
Verbal and written communication skills.
Interpersonal skills.
Multitasking and prioritization skills.

Responsibilities

Provide competitive SRAM design solutions that meet memory design specifications for various product segments.
Design, validate, and characterize Memory Compilers.
Develop Memory Compiler design flows and methodologies.
Collaborate with Intel’s Technology Development group on Design and Technology Co-Optimization to co-define silicon process and physical layout rules.
Interface with customers.