Low Power Verification Engineer, Physical Design

Google•Sunnyvale, CA

5h•$163,000 - $236,000

About The Position

In this role, you’ll help develop custom silicon for Google’s Tensor Processing Unit (TPU), which powers demanding AI/ML applications. You’ll use design and verification expertise to verify complex digital designs, with a focus on TPU architecture and integration within AI/ML-driven systems. The role is part of Google’s AI and Infrastructure team, which delivers AI and infrastructure capabilities at scale, efficiency, reliability, and velocity.

Requirements

Experience in ASIC design and verification.
Experience with physical verification tools, such as DRC and LVS.
Experience with SystemVerilog or other hardware verification languages.
Experience with low-power digital design methodologies.
Experience in design closure on advanced process nodes.
Experience with EDA tools and design methodologies.

Nice To Haves

Experience in low-power digital design methodologies.
Experience in design closure on advanced process nodes.
Experience with Verilog, VHDL, or SystemVerilog, and simulation and verification tools.
Experience developing UVM (Universal Verification Methodology) testbenches.
Experience in Static Timing Analysis (STA) and power analysis.

Responsibilities

Define low-power verification strategies and methodologies for complex ASIC designs.
Author comprehensive low-power verification plans targeting UPF-defined power domains and states.
Develop power-aware testbenches and simulation environments using SystemVerilog and UVM.
Verify power intent using static low-power verification tools such as VC LP or Conformal LP.
Run gate-level simulations with power-aware models to validate power-up and power-down sequences.