Senior Physical Design Verification Engineer
About The Position
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) powers Microsoft’s Intelligent Cloud mission and delivers infrastructure and foundational technologies for Microsoft’s online services and Azure platform. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE designs, develops, manufactures, and packages Microsoft chips, including Azure Cobalt, and supports high-quality, timely, cost-effective, scalable, and sustainable cloud hardware manufacturing. The Senior Physical Design Verification Engineer will support delivery of cutting-edge silicon. The role works with physical design, clock, analog, integration, IP, CAD, tool-vendor, foundry, and other partner teams on physical design verification, chip integration, signoff, and tape-outs at leading-edge technology nodes. It also uses scripting and AI skills to customize tool flows and improve design efficiency and productivity.
Requirements
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 1 year of technical engineering experience; or a master's degree in one of these fields and at least 4 years of technical engineering experience; or a bachelor's degree in one of these fields and at least 5 years of technical engineering experience; or equivalent experience.
- Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
- Provide proof of citizenship, U.S. residency, or other protected status to establish eligibility to access export-controlled information; citizenship will be verified with a valid passport, while lawful permanent residents, refugees, and asylees may use other documents where applicable.
Nice To Haves
- Bachelor’s or master’s degree in Electrical or Computer Engineering/Electrical Engineering.
- At least 5 years of experience in semiconductor chip design or SoC physical design.
- Experience with physical verification EDA tools such as Mentor Calibre and Synopsys ICV.
- Debugging skills for DRC, LVS, ERC, antenna, high-voltage DRC, ESD, and related issues.
- Multiple SoC tape-out experiences on advanced foundry process nodes.
- Understanding of full-chip integration, floor planning, IO RDL, and bump planning.
- Experience and knowledge of physical design flow and industry-standard place-and-route tools such as Fusion Compiler/Innovus and ICC2.
- Understanding of transistor and device basics.
- Proficiency in scripting languages such as Perl, TCL, and Python.
Responsibilities
- Work with top-level and block-level Physical Design Engineers to analyze and fix LVS, DRC, ERC, antenna, and related issues.
- Drive full-chip integration for physical design verification, signoff, and tape-outs on leading-edge technology nodes.
- Collaborate with clock, analog, and integration teams to define, implement, and verify critical chip routing, power delivery, block integration, and other aspects.
- Work with third-party and first-party IP teams to support efficient and timely SoC-IP handshakes.
- Work with the CAD team, tool vendors, foundry, and external partners to develop and validate tools, flows, and runsets.
- Use scripting and AI skills to write and customize tool flows to maximize design efficiency and productivity.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
