Low Power Design Engineer

Apple • Irvine, CA

1d

About The Position

Join Apple’s wireless silicon development team, which develops wireless systems-on-chip (SoCs) with an emphasis on energy-efficient, low-power design and technologies that transform the product-level user experience. In this role, you will design power management logic for complex wireless communication SoCs and contribute to efforts that bring functional products to customers.

You will define SoC power management features to meet product requirements, implement and support verification of power management logic, assist the Power team with power analysis and post-silicon correlation, and provide post-silicon bring-up and debug support.

Requirements

• Bachelor’s degree and a minimum of 10 years of relevant industry experience.
• Proven track record in power, clock, or reset management logic design.
• Proficiency in Verilog.
• Experience with power management logic verification and debugging.
• Understanding of ASIC low-power design techniques.
• Knowledge of CDC, RDC, STA, and UPF.
• Proficiency in scripting languages such as Shell, Perl, or Python.
• Knowledge and experience with common SoC components, such as CPUs, fabrics, and peripherals.
• Strong problem-solving and analytical skills.
• Experience with SoC-level power management logic.
• SoC top-level integration experience.
• System architecture knowledge.
• Post-silicon functional debugging and power correlation experience.

Responsibilities

• Define SoC power management features to meet product requirements.
• Implement power management logic.
• Work with cross-functional (XF) teams to verify power management logic.
• Support the Power team with power analysis and post-silicon correlation efforts.
• Provide post-silicon bring-up and debug support.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior