Low-Power Design Engineer

Voltai • Palo Alto, CA

20h

About The Position

Voltai is developing world models and agents that learn, evaluate, plan, experiment, and interact with the physical world, with a focus on hardware, electronics systems, and semiconductors. The Low-Power Design Engineer will own power intent from architecture through signoff, designing and verifying low-power architectures on real silicon programs with leading semiconductor companies while helping Voltai’s AI learn power-aware design.

Requirements

• 5+ years of low-power design or verification experience on production tapeouts.
• Expert UPF knowledge and experience with power-aware verification.
• Hands-on experience with tools such as VC LP, Conformal Low Power, or PowerArtist.
• Experience with CDC/RDC tools such as SpyGlass, Questa CDC, or similar.
• Python or Tcl scripting.

Nice To Haves

• Experience with mobile, edge, or data-center power management.
• Formal verification of power intent.
• Interest in AI-assisted design tools.

Responsibilities

• Define power architecture and write UPF power intent for SoCs and IP.
• Implement and verify power gating, clock gating, multi-voltage domains, and retention.
• Run power-aware simulation, static low-power checks, and CDC/RDC analysis.
• Partner with RTL, physical design, and signoff teams on power estimation and closure.
• Build automation for power analysis and reporting.
• Evaluate AI-generated power intent and help define what correct looks like.

What This Job Offers

• Job Type: Full-time
• Education Level: No Education Listed