Lead Design Verification Engineer

Chelsea Search Group • Minneapolis, MN

1d

About The Position

The Lead ASIC Design Verification Engineer will establish, staff, and lead the company’s ASIC verification team. This is a hands-on technical leadership role, responsible for architecting and building UVM testbenches for current programs while defining the verification methodology, infrastructure, and hiring plan needed to scale the function. The role serves as the technical authority on verification, establishes coverage-driven sign-off criteria, owns verification schedule and risk for tapeouts, and makes build-versus-buy decisions for VIP, tools, and compute.

The engineer will define verification standards across programs and architect reusable UVM environments for digital SoCs, memory subsystems, secure boot and cryptographic subsystems, and die-to-die interfaces. They will lead verification planning, coverage closure, regression architecture, and quantitative sign-off reporting, and represent verification in design and architecture reviews and with customers, primes, and government stakeholders.

The role also includes building and developing the team, recruiting, setting team structure and hiring profiles, and establishing code review, revision control, documentation, and traceability practices. It remains approximately 50–70% hands-on, including writing SystemVerilog/UVM code, driving constrained-random and directed verification, resolving failures with designers, applying formal and other complementary verification methods, supporting radiation-hardening and fault-tolerance verification, assisting post-silicon bring-up, and maintaining regression infrastructure, simulation licensing, compute utilization, and verification CI.

Requirements

• B.S. in Electrical Engineering, Computer Engineering, or Computer Science.
• 8+ years of ASIC/SoC verification experience, including ownership of verification for at least one production tapeout.
• Expert-level SystemVerilog and UVM skills, including experience architecting UVM environments from scratch.
• Strong command of constrained-random verification, functional coverage, coverage-driven closure, and assertion-based verification with SVA.
• Experience with commercial simulation and coverage tools such as Synopsys VCS/Verdi, Cadence Xcelium, and/or Siemens Questa, and with regression management at scale.
• Working knowledge of digital design and RTL sufficient to read, reason about, and debug design code and discuss design intent versus implementation.
• Scripting proficiency for verification infrastructure using Python, Perl, TCL, and shell; fluency with Git-based workflows and Linux development environments.
• Demonstrated technical leadership through mentoring engineers, leading a verification effort, or owning verification schedule and sign-off for a program.
• Clear written and verbal communication, including presenting verification status and evidence to non-verification stakeholders and customers.
• U.S. Citizenship is required due to ITAR and DFARS requirements applicable to the programs.
• Ability to obtain and maintain a U.S. Government security clearance.

Responsibilities

• Define and own ASIC verification methodology, standards, and sign-off criteria across company programs.
• Architect UVM-based verification environments for digital SoCs, memory subsystems, secure boot and cryptographic subsystems, and die-to-die interfaces.
• Establish reusable verification infrastructure, including base classes, VIP strategy, scoreboarding and checker architecture, UVM RAL, and coverage models.
• Own verification planning, including testplan development, coverage closure strategy, regression architecture, and quantitative sign-off metrics for program and customer stakeholders.
• Represent verification in design and architecture reviews and serve as the technical interface to customers, primes, and government stakeholders on verification approach and evidence.
• Onboard, mentor, and technically develop verification engineers, including junior engineers and design engineers transitioning into verification.
• Define verification team structure, roles, and hiring profiles; participate in recruiting, interviewing, and selection.
• Establish and enforce code review, revision control, documentation, and traceability practices for defense-qualified deliverables.
• Allocate verification effort across concurrent programs and communicate resourcing risk to engineering and program management.
• Write SystemVerilog/UVM testbench code, sequences, agents, and functional coverage models; maintain an approximately 50–70% hands-on contribution.
• Drive constrained-random and directed verification to coverage closure; triage failures and work with designers on root-cause resolution.
• Apply formal property verification, assertion-based verification (SVA), gate-level simulation, and emulation/prototyping where appropriate.
• Support verification of radiation-hardening and fault-tolerance features, including TMR structures, error detection and correction, and SEU/SET mitigation behavior.
• Support post-silicon bring-up by correlating silicon behavior to pre-silicon models and closing verification gaps.
• Own and maintain regression infrastructure, simulation licensing and compute utilization, and verification CI.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior