Senior Lead Engineer - Design Verification

Altera•San Jose, CA

23h•$231,500 - $330,000•Onsite

About The Position

Altera is seeking a Senior Lead Engineer - Design Verification to provide hands-on technical leadership for verification of next-generation FPGA, programmable SoC, and platform solutions. This senior individual-contributor role shapes verification architecture, methodology, and execution for complex digital subsystems and full-chip integrations. The role defines scalable verification strategies, develops reusable verification environments, and drives coverage-driven closure from early architecture through silicon and product readiness. It requires deep SystemVerilog/UVM expertise, strong technical judgment, a high bar for verification quality, and the ability to influence engineering execution across global, cross-functional teams. The listed salary range is $231,500–$330,000 USD for the Bay Area, California only. Actual salary may vary based on location and job-related knowledge, skills, experience, and training. Incentive opportunities are also offered based on individual and company performance. The employer uses artificial intelligence to screen, assess, or select applicants. Applicants must be eligible for any required U.S. export authorizations.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
15+ years of relevant experience in design verification for FPGA, ASIC, SoC, or semiconductor products.
Demonstrated technical leadership delivering verification for complex digital subsystems or products from architecture through RTL verification, integration, full-chip verification, and hardware or silicon validation.
Deep expertise in SystemVerilog and UVM, including constrained-random verification, assertions, self-checking environments, testbench architecture, functional coverage, and coverage-driven closure.
Experience creating reusable verification IP, UVM frameworks, testbench components, or methodology adopted across multiple blocks, teams, or programs.
Experience verifying high-performance digital architectures such as networking or packet-processing datapaths, memory subsystems, on-chip interconnect, PCIe/CXL, Ethernet, high-speed I/O, or programmable acceleration.
Strong understanding of RTL design, microarchitecture, simulation, debug, formal or static verification concepts, and hardware development flows.
Experience with regression management, simulation build and execution flows, test automation, and data-driven verification reporting.
Ability to collaborate and influence across architecture, RTL design, CAD, emulation, firmware/software, system validation, and product engineering organizations.
Strong written and verbal communication skills, including communicating verification strategy, risk, closure status, and technical recommendations to diverse audiences.

Nice To Haves

Advanced degree in a related technical discipline.
Experience verifying FPGA architectures, programmable-logic devices, configurable interconnect, SmartNICs, IPUs, SoCs, or data-center acceleration platforms.
Experience with C/C++, SystemC, Python, Tcl, Perl, or shell scripting for reference models, automation, testbench infrastructure, or verification productivity.
Experience with formal verification, low-power verification, CDC/RDC analysis, performance verification, or hardware-accelerated verification environments.
Experience with full-chip verification, processor-based test development, firmware/software co-verification, or post-silicon debug.
Experience leading verification methodology or mentoring engineers in a matrixed engineering environment.
A record of innovation through patents, publications, standards contributions, or sustained methodology leadership.

Responsibilities

Lead verification architecture, planning, and execution for complex FPGA, programmable SoC, and infrastructure-class subsystems, including block, subsystem, and full-chip verification.
Define verification plans that translate architectural intent and product requirements into measurable functional, performance, resilience, and coverage objectives.
Architect and develop scalable, reusable SystemVerilog/UVM verification environments, verification IP, scoreboards, reference models, constrained-random stimulus, checkers, and coverage models.
Establish and advance verification methodology, coding standards, testbench guidelines, regression practices, and automation to improve consistency, quality, reuse, debug efficiency, and predictability.
Drive verification closure using functional, code, assertion, and cross coverage; identify coverage gaps, evaluate risk, and ensure readiness against defined exit criteria.
Partner with architecture and RTL design teams to clarify specifications, identify verification risks early, review microarchitecture, and resolve complex functional or performance issues.
Lead debug of difficult simulation, integration, and system-level failures; perform root-cause analysis and drive timely resolution across design, verification, firmware, and validation teams.
Develop and maintain scalable simulation, regression, build, and reporting infrastructure.
Collaborate with emulation, FPGA prototyping, physical design, CAD, firmware, software, board, and post-silicon teams to carry verification intent through implementation, bring-up, and product delivery.
Provide technical mentorship and verification leadership through methodology, test-plan, and code reviews, and hands-on guidance to engineers across the organization.