Hardware ASIC Packaging SI/PI Simulation and Design Lead (Remote)

Cisco•San Jose, CA

2d•$186,900 - $267,700•Remote

About The Position

Cisco Silicon One is seeking a Signal and Power Integrity Technical Lead to develop next-generation ASIC packaging for deployment across Cisco platforms. The role focuses on defining, designing, and verifying ASIC packages, including advanced 2.5D packaging and heterogeneous system integration. The lead will develop design rules for ultra-high-speed signaling and analyze substrate signal and power integrity. Working with layout teams, system partners, vendors, and design leads, the role will address technical challenges across interposers, substrates, and PCBs. Responsibilities also include package design and release, simulation and post-layout analysis, defining methods and tools for complex ASIC/package development, and contributing to chip architecture and high-performance ASIC design. The role supports and mentors engineers and promotes design reviews, postmortems, and continuous improvement across engineering teams. The role is based in Cisco’s San Jose, California office, with a preference for candidates able to commute onsite four to five days per week; fully remote candidates may also be considered.

Requirements

Bachelor’s degree in Electrical Engineering and 8 or more years of relevant signal and power integrity experience; or a master’s degree in Electrical Engineering and 6 or more years; or a PhD in Electrical Engineering and 3 or more years.
Experience applying high-speed design principles—including transmission line theory, electromagnetics, scattering parameters, and impedance network analysis—to 56G PAM4 SerDes architectures, channel modeling, and BER prediction.
Experience with pre- and post-layout signal and power integrity simulations using industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS.
Experience conducting detailed layout reviews and physical design validation using tools such as Cadence APD and Ansys EM flows to ensure signal performance and mitigate crosstalk.
Experience using SPICE for circuit-level analysis, signal modeling, and performance validation.

Nice To Haves

Ability to articulate ideas and technical concepts to diverse audiences verbally and in writing.
Experience with high-bandwidth memory (HBM) or high-speed memory interface signal integrity.
Experience with die-to-die interfaces, such as UCIe or proprietary interfaces.
Experience with advanced packaging, such as CoWoS, EMIB, or interposer-based designs, including signal and power integrity analysis of 2.5D ASIC packaging.
Experience with Vector Network Analysis.
Experience with IBIS.

Responsibilities

Develop, document, and implement design rules for ultra-high-speed signaling while meeting product power, performance, and area goals.
Analyze substrate signal integrity and power integrity, and collaborate with layout teams on solutions across interposers, substrates, and PCBs.
Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and resolve complex technical issues using advanced technology design rules.
Define processes, methods, and tools for complex ASIC/package design and implementation.
Lead or participate in chip architecture discussions and the definition, architecture, and design of high-performance ASICs, including reviews of intricate IC and analog/mixed-signal circuit designs.
Mentor and support the signal integrity team and junior engineers, and influence packaging and hardware teams to meet technical specifications and develop innovative solutions.
Promote design reviews, postmortems, and continuous improvement across multidisciplinary engineering teams.

Benefits

Medical, dental, and vision insurance, subject to plan eligibility.
401(k) plan with a Cisco matching contribution.
Paid parental leave.
Short- and long-term disability coverage.
Basic life insurance.
Potential eligibility for Cisco restricted stock unit grants, subject to continued employment and vesting terms.
Paid holidays and a floating holiday for non-exempt employees.
Paid birthday time off, year-end holiday shutdown, and personal wellness days.
Paid vacation or flexible vacation time off, depending on employee classification.
Paid sick time, with the ability to carry forward up to 80 unused hours.
Additional paid time away may be requested for critical or emergency family issues.
Optional paid volunteer days.
Eligibility for annual bonuses for non-sales roles, subject to Cisco policies.