Hardware ASIC Packaging SI/PI Simulation and Design Lead (Remote)

Cisco•San Jose, CA

12h

About The Position

Cisco Silicon One is seeking a Signal and Power Integrity Technical Lead to develop next-generation ASIC packaging for deployment across Cisco platforms. The role defines, designs, and verifies ASIC packaging, develops design rules for ultra-high-speed signaling, and analyzes substrate signal and power integrity to help meet product power, performance, and area goals. The position works closely with layout teams and partners on solutions spanning interposers, substrates, and PCBs. The lead designs and documents ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting. The role collaborates with system partners, vendors, and design leads to resolve complex technical issues; defines processes, methods, and tools for complex ASIC/package development; and participates in chip architecture and high-performance ASIC design discussions. The lead also mentors engineers, influences packaging and hardware teams, and promotes design reviews, postmortems, and continuous improvement across multidisciplinary teams. The role is based in Cisco’s San Jose, California office, with a preference for candidates able to commute onsite four to five days per week; fully remote candidates may also be considered.

Requirements

Bachelor’s degree in Electrical Engineering and 8 or more years of relevant signal and power integrity experience; or a Master’s degree and 6 or more years; or a PhD and 3 or more years.
Experience with high-speed design principles, including transmission line theory, electromagnetics, scattering parameters, and impedance network analysis, applied to 56G PAM4 SerDes architectures, channel modeling, and BER prediction.
Experience with pre- and post-layout SI/PI simulations using industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS.
Experience conducting detailed layout reviews and physical design validation using tools such as Cadence APD and Ansys EM flows to ensure signal performance and mitigate crosstalk.
Experience using SPICE for circuit-level analysis, signal modeling, and performance validation.

Nice To Haves

Ability to articulate ideas and technical concepts to diverse audiences verbally and in writing.
Experience with high-bandwidth memory (HBM) or high-speed memory interface signal integrity.
Experience with die-to-die interfaces such as UCIe or proprietary interfaces.
Experience with advanced packaging, including CoWoS, EMIB, and interposer-based designs, and SI/PI analysis of 2.5D ASIC packaging.
Experience with Vector Network Analysis.
Experience with IBIS.

Responsibilities

Develop, document, and implement design rules for ultra-high-speed signaling while ensuring product power, performance, and area goals are met.
Analyze substrate signal integrity (SI) and power integrity (PI), and collaborate with layout teams on solutions across interposers, substrates, and PCBs.
Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
Collaborate with system partners, vendors, and design leads to achieve power and signal integrity goals and resolve complex technical issues using advanced technology design rules.
Define processes, methods, and tools for complex ASIC/package development and implementation.
Lead or participate in chip architecture discussions and the definition, architecture, and design of high-performance ASICs, including reviews of intricate IC and analog/mixed-signal circuit designs.
Mentor and support the signal integrity team and junior engineers, and influence packaging and hardware teams.
Promote design reviews, postmortems, and continuous improvement across multidisciplinary engineering teams.

Benefits

Medical, dental, and vision insurance.
401(k) plan with a Cisco matching contribution.
Paid parental leave.
Short- and long-term disability coverage.
Basic life insurance.
Paid holidays and a floating holiday for non-exempt employees.
Paid birthday day off, year-end holiday shutdown, and personal wellness days.
Vacation time, including a flexible vacation time off program for exempt employees.
Sick time off, with unused sick time carryover subject to the stated limit.
Additional paid time away may be requested for critical or emergency family issues.
Optional paid volunteer days.
Annual bonuses may be available for non-sales roles, subject to Cisco policies.
Employees may be eligible for Cisco restricted stock unit grants, subject to vesting conditions.