Hardware ASIC Packaging SI/PI Simulation and Design Lead (Remote)

Cisco•San Jose, CA

4d•$186,900 - $267,700•Remote

About The Position

This Hardware Engineering position is located in San Jose, CA, and is open to remote applicants residing within the United States. The Cisco Silicon One team is seeking a highly qualified Signal and Power Integrity Technical Lead to help define, design, and verify ASIC packaging for next-generation ASICs to be deployed in a range of Cisco platforms. This role involves developing design rules for ultra-high-speed signaling, analyzing substrate signal and power integrity, designing ASIC packages, and collaborating with various teams and vendors to resolve complex technical issues. The lead will also define processes, methods, and tools for ASIC/package development, participate in chip architecture discussions, and mentor junior engineers.

Requirements

Bachelor's degree in Electrical Engineering and 8+ years of relevant signal and power integrity experience, or Master's degree in Electrical Engineering and 6+ years of relevant signal and power integrity experience, or PhD in Electrical Engineering and 3+ years of relevant signal and power integrity experience.
Experience with high-speed design principles, including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis, applied to 56G PAM4 SerDes architectures, channel modeling, and BER prediction.
Experience with pre- and post-layout signal and power integrity (SI/PI) simulations using industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS.
Experience conducting detailed layout reviews and physical design validation using tools such as Cadence APD and Ansys EM flows to ensure signal performance and crosstalk mitigation.
Experience with SPICE for circuit-level analysis, signal modeling, and performance validation.

Nice To Haves

Skilled in articulating ideas and technical concepts to diverse audiences, both verbally and in writing.
Experience with high-bandwidth memory (HBM) or high-speed memory interface SI.
Experience with die-to-die interfaces (UCIe or proprietary).
Experience with advanced packaging (CoWoS, EMIB, interposer-based designs), including SI/PI analysis of 2.5D ASIC packaging.
Experience with Vector Network Analysis.
Experience with IBIS.

Responsibilities

Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products.
Analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions across interposer, substrate, and PCB.
Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules.
Define the processes, methods, and tools for the design and implementation of complex ASIC/package developments.
Lead or participate in chip architecture discussions and the definition, architecture, and design of high-performance ASICs, including reviews of intricate IC and analog/mixed-signal circuit designs.
Mentor and support the signal integrity team, junior engineers, and influence packaging/hardware teams, ensuring all technical specifications and innovative solutions are met.
Develop and promote a culture of design reviews, postmortems, and continuous improvement across multi-disciplined engineering teams.

Benefits

medical, dental and vision insurance
a 401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees (non-exempt)
flexible vacation time off program (exempt)
80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
Optional 10 paid days per full calendar year to volunteer
annual bonuses (for non-sales roles)
performance-based incentive pay (for sales roles)