Hardware ASIC Packaging SI/PI Simulation and Design Lead (Remote)

Cisco•San Jose, CA

1d•Remote

About The Position

Cisco Silicon One is seeking a Signal and Power Integrity Technical Lead to develop next-generation ASIC packaging for deployment across Cisco platforms. The role defines, designs, and verifies ASIC packaging, helping ensure ultra-high-speed signaling meets power, performance, and area goals. It analyzes substrate signal and power integrity and works with layout teams to optimize interposer, substrate, and PCB solutions. The position also develops ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting. The lead collaborates with system partners, vendors, and design leads to achieve combined power and signal integrity and resolve complex technical issues. The role defines processes, methods, and tools for complex ASIC and package development; contributes to chip architecture and high-performance ASIC design discussions; and reviews intricate IC and analog/mixed-signal circuit designs. It also mentors signal integrity and junior engineers, influences packaging and hardware teams, and promotes design reviews, postmortems, and continuous improvement across multidisciplinary engineering teams. The position is based in San Jose, California, and is open to remote applicants residing in the United States.

Requirements

Bachelor's degree in Electrical Engineering and 8 or more years of relevant signal and power integrity experience; or a Master's degree in Electrical Engineering and 6 or more years; or a Ph.D. in Electrical Engineering and 3 or more years.
Experience with high-speed design principles, including transmission line theory, electromagnetics, scattering parameters, and impedance network analysis, applied to 56G PAM4 SerDes architectures, channel modeling, and BER prediction.
Experience with pre- and post-layout SI/PI simulations using industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS.
Experience conducting detailed layout reviews and physical design validation using tools such as Cadence APD and Ansys EM flows to ensure signal performance and crosstalk mitigation.
Experience with SPICE for circuit-level analysis, signal modeling, and performance validation.

Nice To Haves

Ability to articulate ideas and technical concepts clearly to diverse audiences, verbally and in writing.
Experience with high-bandwidth memory (HBM) or high-speed memory interface signal integrity.
Experience with die-to-die interfaces such as UCIe or proprietary interfaces.
Experience with advanced packaging such as CoWoS, EMIB, or interposer-based designs, including SI/PI analysis of 2.5D ASIC packaging.
Experience with Vector Network Analysis.
Experience with IBIS.

Responsibilities

Develop, document, and implement design rules for ultra-high-speed signaling while meeting product power, performance, and area goals.
Analyze substrate signal integrity and power integrity, and collaborate with layout teams on solutions across interposer, substrate, and PCB.
Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
Collaborate with system partners, vendors, and design leads to achieve power and signal integrity goals and resolve complex technical issues using advanced technology design rules.
Define processes, methods, and tools for complex ASIC and package design and implementation.
Lead or participate in chip architecture discussions and the definition, architecture, and design of high-performance ASICs, including reviews of intricate IC and analog/mixed-signal circuit designs.
Mentor and support the signal integrity team and junior engineers, and influence packaging and hardware teams to meet technical specifications and deliver innovative solutions.
Promote design reviews, postmortems, and continuous improvement across multidisciplinary engineering teams.

Benefits

Medical insurance
Dental insurance
Vision insurance
401(k) plan with Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Paid holidays
Floating holiday for non-exempt employees
Paid day off for employee's birthday
Paid year-end holiday shutdown
Paid personal wellness days
Paid vacation or flexible vacation time off, depending on employee classification
Sick time off
Additional paid time away may be requested for critical or emergency family issues
Optional paid volunteer days
Annual bonuses for eligible non-sales roles
Potential Cisco restricted stock unit grants