Front End Design Verification Engineer

Tenstorrent•Santa Clara, CA

9d•Remote

About The Position

Tenstorrent is seeking a Front End Design Verification Engineer to join their team and contribute to the verification of the fetch unit for their next-generation high-performance RISC-V CPU cores. This role involves working on the logic responsible for instruction fetch, prediction, decode, and dispatch. The engineer will collaborate with CPU architects and RTL designers to develop verification strategies, create tests, debug failures, and ensure the front end functions correctly across various workloads and corner cases. This position offers an opportunity to significantly impact the performance and correctness of a high-performance out-of-order CPU. The role is remote and based in North America or Spain. Tenstorrent welcomes candidates at various experience levels, and the final level will be determined during the interview process.

Requirements

6+ years of experience in design verification for CPUs, SoCs, ASICs, or other complex digital designs.
Strong experience with SystemVerilog and UVM, including constrained-random testing, assertions, functional coverage, and testbench development.
Solid understanding of CPU architecture, with familiarity in areas such as pipelines, instruction fetch/decode, branch prediction, speculative execution, or out-of-order execution.
Experience debugging RTL and simulation failures using waveforms and standard simulation/debug tools.
Strong programming skills in C/C++ and/or Python.
Ability to collaborate effectively across architecture, RTL, DV, and software teams.

Nice To Haves

Comfortable working with CPU front-end concepts such as instruction fetch, branch prediction, instruction decode, queues, and dispatch.
A strong problem solver who can move between specifications, RTL, simulations, and waveforms to identify root causes.
Collaborative and proactive, with the ability to work closely with architects, RTL designers, and other DV engineers.
Curious about high-performance CPUs and excited to learn how microarchitectural decisions impact real-world processor performance.

Responsibilities

Work on the logic responsible for keeping the processor fed with the right instructions at the right time—from instruction fetch and prediction through decode and dispatch.
Partner closely with CPU architects and RTL designers to develop verification strategies.
Create sophisticated tests.
Debug complex failures.
Ensure the front end behaves correctly across a wide range of workloads and corner cases.