Front End Design Engineer

Apple • Austin, TX

2d • Onsite

About The Position

Apple Inc. has an available Front End Design Engineer position in Austin, Texas. The role converts RTL designs into netlists using industry-standard synthesis tools and optimizes power, performance, and area by experimenting with synthesis recipes and improving synthesis methodologies. The engineer understands Verilog and SystemVerilog RTL, correlates RTL to gate-level circuits, and guides the development of optimal RTL solutions.

The position performs clock and reset domain crossing checks, lint checks, logical equivalence checks, and static timing analysis. It also analyzes RTL simulation waveforms to understand design intent and signal activity, supports ECO generation, and collaborates with internal R&D teams. The position is 40 hours per week.

Requirements

• Master’s degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, or a related field.
• One year of experience in the job offered or a related occupation.
• Experience and/or education synthesizing RTL designs into netlists using Design Compiler or Genus.
• Experience and/or education understanding RTL and making RTL updates for PPA.
• Experience and/or education creating unit testbenches to verify RTL updates.
• Experience and/or education working with simulation waveforms to understand design intent.
• Experience and/or education performing static timing analysis and achieving timing closure.
• Experience and/or education performing lint checks to ensure RTL quality.
• Experience and/or education performing clock domain crossing checks.
• Experience and/or education performing reset domain crossing checks.

Responsibilities

• Convert RTL designs into netlists using industry-standard RTL synthesis tools.
• Optimize power, performance, and area by experimenting with synthesis recipes and enhancing synthesis methodologies.
• Understand Verilog and SystemVerilog RTL, correlate it to gate-level circuits, and guide development of optimal RTL solutions.
• Perform clock and reset domain crossing checks and lint checks.
• Perform logical equivalence checks to verify generated netlists and support ECO generation activities.
• Perform static timing analysis to identify critical paths and propose solutions involving physical implementation and microarchitectural optimizations.
• Analyze RTL simulation waveforms to understand design intent and common signal activity patterns.
• Collaborate effectively with internal R&D teams.

What This Job Offers

• Job Type: Full-time