Director, Front End Design

kepler•San Jose, CA

8d•$270,000 - $310,000

About The Position

Kepler is seeking a highly experienced Director, Front-End Design to own pre-silicon RTL design and implementation for its products. This leadership role drives execution across RTL design, IP integration, physical design, verification, and packaging, from micro-architecture definition through tapeout and post-silicon validation. The Director will establish design execution strategies and standards, lead cross-functional integration, plan bring-up and validation, and build and mentor a team of RTL design and IP engineers.

Requirements

B.Tech, M.Tech, MS, or PhD in EE, Electronics, VLSI Design, or a related field.
15+ years of hands-on VLSI front-end RTL design experience with multiple successful SoC/ASIC tapeouts.
Deep expertise in RTL design and micro-architecture using SystemVerilog/Verilog, with strong PPA optimization skills.
Strong knowledge of low-power design methods, including UPF/CPF, clock and power gating, retention, and isolation.
Hands-on experience with synthesis flows and timing closure.
Skilled with industry-standard lint, CDC/RDC, and formal verification tools.
Solid knowledge of DFT methods, including scan insertion, ATPG, MBIST, and JTAG.
Strong understanding of SoC-level challenges, including clock domain crossings, reset architecture, power domains, and memory subsystems.
Knowledge of industry-standard on-chip and memory protocols.
Experience with post-silicon validation, debug, and production test correlation.
Strong scripting skills in Python, Perl, Shell, and Tcl.
Excellent leadership and communication skills, with a proven ability to lead teams in a fast-paced environment.

Nice To Haves

Familiarity with AI workloads and their memory demands.
Background in high-bandwidth memory subsystem design.
Exposure to hardware/software co-design (TLM/SystemC).
Understanding of how RTL interacts with physical design and PD-driven RTL optimization.
Experience with 3D innovations.
Experience with emulation platforms.
Familiarity with ML-assisted design optimization tools.
Prior startup experience with lean teams and aggressive timelines.

Responsibilities

Own pre-silicon RTL design end to end, from micro-architecture through RTL freeze, synthesis handoff, and tapeout signoff.
Define design execution strategy, including RTL coding guidelines, partitioning, clock and reset architecture, low-power strategy, and DFT integration.
Track design execution metrics, including RTL quality, lint/CDC status, and synthesis QoR, and present them at milestone reviews.
Drive IP integration and ensure IP quality meets integration standards.
Work with architecture, verification, physical design, DFT, and software teams to enable smooth cross-functional integration.
Set RTL design best practices, review standards, and sign-off infrastructure.
Lead bring-up planning and post-silicon validation, debug, and qualification.
Build, lead, and mentor a team of RTL design and IP engineers.