Front End Design Engineer

Apple • Austin, TX

1d • Onsite

About The Position

Apple Inc. has an available Front End Design Engineer position in Austin, Texas. The role converts RTL designs into netlists using industry-standard RTL synthesis tools and optimizes power, performance, and area by experimenting with synthesis recipes and enhancing existing synthesis methodologies. The engineer understands Verilog and SystemVerilog RTL, correlates it to gate-level circuits, and guides the development of optimal RTL solutions.

The position performs Clock and Reset Domain Crossing (CDC/RDC) checks and lint checks, logical equivalence checks, and static timing analysis (STA). It supports ECO generation, identifies critical paths, and proposes solutions involving physical implementation and microarchitectural optimizations. The engineer analyzes RTL simulation waveforms using industry-standard simulator tools to understand design intent and common signal activity patterns, and collaborates with internal R&D teams. The role is 40 hours per week.

Requirements

• Master's degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, or a related field.
• At least 1 year of experience in the job offered or a related occupation.
• Experience or education synthesizing RTL designs using Design Compiler or Genus into netlists.
• Experience or education understanding RTL and making RTL updates for PPA.
• Experience or education creating unit testbenches to verify RTL updates.
• Experience or education working with simulation waveforms to understand design intent.
• Experience or education performing Static Timing Analysis (STA) and achieving timing closure.
• Experience or education performing lint checks to ensure RTL quality.
• Experience or education performing Clock Domain Crossing (CDC) checks.
• Experience or education performing Reset Domain Crossing (RDC) checks.

Responsibilities

• Convert RTL designs into netlists using industry-standard RTL synthesis tools.
• Optimize power, performance, and area by experimenting with synthesis recipes and improving existing synthesis methodologies.
• Understand Verilog and SystemVerilog RTL, correlate it to gate-level circuits, and guide the development of optimal RTL solutions.
• Perform CDC and RDC checks to assess design robustness against metastability-related problems.
• Perform lint checks to ensure RTL quality.
• Perform logical equivalence checks to verify generated netlists and support ECO generation activities.
• Perform static timing analysis to identify critical paths and propose physical implementation or microarchitectural optimizations.
• Analyze RTL simulation waveforms to understand design intent and common signal activity patterns.
• Collaborate with internal R&D teams.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level