Front End Design Verification Engineer
About The Position
Tenstorrent is looking for a Front End Design Verification Engineer to help verify the fetch unit for their next generation of high-performance RISC-V CPU cores. This role involves working on the logic responsible for instruction fetch, prediction, decode, and dispatch. The engineer will collaborate with CPU architects and RTL designers to develop verification strategies, create tests, debug failures, and ensure the front end functions correctly across various workloads and corner cases. This is an opportunity to significantly impact the performance and correctness of a high-performance out-of-order CPU.
Requirements
- 6+ years of experience in design verification for CPUs, SoCs, ASICs, or other complex digital designs.
- Strong experience with SystemVerilog and UVM, including constrained-random testing, assertions, functional coverage, and testbench development.
- Solid understanding of CPU architecture, with familiarity in areas such as pipelines, instruction fetch/decode, branch prediction, speculative execution, or out-of-order execution.
- Experience debugging RTL and simulation failures using waveforms and standard simulation/debug tools.
- Strong programming skills in C/C++ and/or Python.
- Ability to collaborate effectively across architecture, RTL, DV, and software teams.
- Eligibility to access U.S. export-controlled technology, subject to U.S. export laws and regulations.
Nice To Haves
- Comfortable working with CPU front-end concepts such as instruction fetch, branch prediction, instruction decode, queues, and dispatch.
- A strong problem solver who can move between specifications, RTL, simulations, and waveforms to identify root causes.
- Collaborative and proactive, with the ability to work closely with architects, RTL designers, and other DV engineers.
- Curious about high-performance CPUs and excited to learn how microarchitectural decisions impact real-world processor performance.
Responsibilities
- Verify the fetch unit for next generation of high-performance RISC-V CPU cores.
- Work on logic responsible for instruction fetch, prediction, decode, and dispatch.
- Partner closely with CPU architects and RTL designers to develop verification strategies.
- Create sophisticated tests.
- Debug complex failures.
- Ensure the front end behaves correctly across a wide range of workloads and corner cases.
Benefits
- Highly competitive compensation package
- Benefits
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
Education Level
No Education Listed
