Director, ASIC Verification
About The Position
The Director of ASIC Verification will lead verification strategy, sign-off, and team development while remaining deeply hands-on as a verification engineer. The role owns end-to-end verification methodology and execution across silicon, IP, and subsystems, including tape-out sign-off and post-silicon bring-up support. It involves architecting and authoring verification environments and test plans, reviewing testbench code, closing coverage, and personally debugging complex protocol, coverage, and bring-up issues. The director will recruit, lead, and develop a technically strong verification organization and communicate verification readiness, metrics, and risks to engineering leadership. The position is performed onsite at the company's Santa Clara, California office. The company describes an early-stage environment focused on high-performance computing architecture, with opportunities for ownership and influence over product direction and execution.
Requirements
- Bachelor's or master's degree in Electrical Engineering, Computer Engineering, or a related field.
- At least 8 years of progressive ASIC/SoC verification experience.
- At least 5 years leading verification teams.
- Demonstrated experience writing verification code, building testbenches, and closing coverage.
- Experience with multiple tape-outs in advanced process nodes, with ownership of both deep technical work and sign-off.
- Hands-on experience with high-speed protocol IP such as Ethernet, UCIe, UALink, or comparable protocols.
- Fluency across the ASIC/SoC lifecycle, from microarchitecture through tape-out, on designs integrating interconnect, I/O, and memory subsystems.
- Executive communication skills and proven ability to manage risk, escalations, budget, and headcount on startup timelines.
Nice To Haves
- PhD in Electrical Engineering, Computer Engineering, or a related field.
- Experience building a verification team from zero at an early-stage startup while personally delivering milestones.
- Hands-on post-silicon bring-up, debug, and validation leadership.
- AI or datacenter accelerator background and familiarity with LLM memory/dataloader bottlenecks.
- Knowledge of DFT and its interaction with front-end verification.
Responsibilities
- Own end-to-end verification strategy and methodology, including UVM, formal verification, emulation, and coverage-driven closure.
- Lead tape-out sign-off for silicon, IP, and subsystems, and support post-silicon bring-up, including test-vector generation.
- Architect and author verification environments and test plans.
- Review testbench code in detail and personally debug challenging protocol, coverage, and bring-up issues.
- Recruit, lead, and develop the verification organization.
- Present verification readiness, metrics, and risk posture to engineering leadership.
- Manage risk, escalations, budget, and headcount on startup timelines.
Benefits
- Performance-based bonus and early-stage equity grant.
- 100% employer-paid health, dental, and vision coverage for the employee and dependents.
- 401(k) match with immediate vesting and access to financial advisors.
- 100% employer-paid life, disability, and AD&D insurance.
- Fitness stipend and wellness and mental health perks.
- 20 vacation days and 15 company holidays, including 3 floating days.
- Daily lunch stipend.
- Enterprise-level Claude and ChatGPT access with a generous token budget.
- On-site parking and EV charging at the Santa Clara and Cambridge offices.
- On-site fitness center in Santa Clara and gym discounts near the Cambridge office.
- Visa sponsorship and relocation assistance to an office hub.
- Collaborative, continuous-learning environment.
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What This Job Offers
Job Type
Full-time
Career Level
Director
